F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 2/03/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
1. Introduction x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Hardware States and Configuration Profiles 4.4. Nios® -Based Dynamic Reconfiguration Flow
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm
1. Introduction
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP

6.1. Dynamic Reconfiguration New Trigger

Table 13.   dyn_rcfg_dr_trigger_reg
Offset 0x00
Addressing Mode 32-bits
Description Dynamic reconfiguration control and status register.
Table 14.   dyn_rcfg_dr_trigger_reg Field Description
Bit Type Reset Description
31:2 RO 0 Reserved
1 RO   Ready for New Trigger
Indicates whether the DR IP is ready to take in a new Trigger Reconfiguration request. Host software must poll for the readiness status before triggering a new request through Trigger Reconfiguration.
  • 0: Not ready
  • 1: Ready
0 RWC 0 Trigger Reconfiguration

When set to value 1 by host software, Nios® core starts executing the dynamic reconfiguration flow in which the relevant DR CSR fields are read to check for user DR intention, followed by various other steps.

Hardware clears this bit to value 0’ after the triggering event has been captured successfully by Nios® core.

When read by software, the value is always 0. Writing a value of 0 to this register has no effect.

Do not program this field to value of 1 when Ready For Next Trigger is set to 0.

Note: An invalid programming sequence is if the corresponding channel dyn_rcfg_dr_txch2reconfig_busy_reg/dyn_rcfg_dr_rxch2reconfig_busy_reg bits are programmed to value of 1 and their associated BUSY bits are value of 1 when this field is programmed. In the case, the results are indeterminate.
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