F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 2/03/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
1. Introduction x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Hardware States and Configuration Profiles 4.4. Nios® -Based Dynamic Reconfiguration Flow
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm
1. Introduction
2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP

4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles

You configure the Dynamic Reconfiguration IP along with a respective protocol IP through the appropriate IP graphical user interface (GUI) settings. Based on the IP settings, RTL connections in the design, and the required QSF settings, the Intel® Quartus® Prime software generates the required programming file sets. The generated programming file sets include the connection information and the MIF file.
To generate a dynamic reconfiguration design, follow these steps:
  1. Create an Intel® Quartus® Prime project.
  2. In the Intel® Quartus® Prime IP Catalog, locate the respective required protocol IP.
  3. Configure the protocol IP instance with the targeted settings.
  4. Generate the protocol IP.
  5. If your design requires multiple protocol IPs, repeat steps 2 through 4 for each protocol IP.
  6. In the IP Catalog, locate the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP (Dynamic Reconfiguration IP).
  7. Configure the Dynamic Reconfiguration IP instance with the targeted settings.
  8. Generate the Dynamic Reconfiguration IP.
  9. Instantiate the protocol IP(s) and a Dynamic Reconfiguration IP in your RTL. For RTL connections examples, refer to the design examples generated per the F-Tile Dynamic Reconfiguration Design Example User Guide
    Note: Each F-tile only supports a single Dynamic Reconfiguration IP instance.
  10. Enter the dynamic reconfiguration IP-specific .qsf settings such as the reconfiguration groups and others. For more information, refer to Dynamic Reconfiguration QSF Settings.
  11. Once your project compiles, the Intel® Quartus® Prime software generates a new top project file and other collaterals required by your design, including a MIF file containing the delta programming sequences.
Figure 2. Dynamic Reconfiguration Design Generation Flow
The diagram below illustrates the RTL connections for a dynamic reconfiguration design:
Figure 3. RTL Connections in Dynamically Reconfigured Design
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