F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 8/17/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 3.2. PMA/FEC Direct PHY Multirate Design Example: Registers
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
3.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 3.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
4. Detailed Description for Ethernet Multirate Design Example x
4.1. Ethernet Multirate Design Example: Functional Description 4.2. Ethernet Multirate Design Example: Registers
4.1. Ethernet Multirate Design Example: Functional Description x
4.1.1. Ethernet Multirate Design Example: Simulation Testbench 4.1.2. Ethernet Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description 5.2. Ethernet to CPRI Design Example: Registers
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

1.2.2. Ethernet Multirate Design Example Parameters

Figure 4. Ethernet Multirate Example Design Tab
Table 3.  Ethernet Multirate Design Example Parameters
Parameters Value Description
Select Protocol/mode

Ethernet

 Select the IP protocol for dynamic reconfiguration.
Select Base Variant

25G-1

25G-1 PTP

100G-4

100G-4 PTP

400G-8

400G-8 PTP

FHT 400G-4

 Select the configuration of base variant for dynamic reconfiguration.
Example Design Files Simulation

Synthesis

 Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example.
Generated File Format Verilog

VHDL

 Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator.
Target Development Kit None

Intel Agilex® 7 I-Series Transceiver-SoC Development Kit

Target development kit option specifies the target device used to generate the project.
Enable auto-negotiation and link training Options

On

Off

 Enables auto-negotiation and link training for the Ethernet port.

You must instantiate the F-Tile Auto-Negotiation and Link Training FPGA IP to support this feature.
Level Two Title