Visible to Intel only — GUID: gut1613681213363
Ixiasoft
2.1. Clock Signals
2.2. Reset Signals
2.3. TX MII Interface (64b/66b)
2.4. RX MII Interface (64b/66b)
2.5. Status Interface for 64b/66b Line Rate
2.6. TX Interface (8b/10b)
2.7. RX Interface (8b/10b)
2.8. Status Interface for 8b/10b Line Rate
2.9. Serial Interface
2.10. CPRI PHY Reconfiguration Interface
2.11. Datapath Avalon Memory-Mapped Interface
2.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: gut1613681213363
Ixiasoft
2.8. Status Interface for 8b/10b Line Rate
This section lists the status ports for the CPRI PHY 8b/10b line rate. Each CPRI PHY channel has its own status port.
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
o_rx_patterndetect | 1 | o_rx_clkout2 | The IP core asserts this signal to indicate that K28.5 has been detected in the current word boundary of o_rx_d or o_rx_c and the received data from the RX PMA achieved the word alignment. This interface should be observed in conjunction with o_rx_disperr and i_rx_errdetect. |
o_rx_disperr[1:0] | 2 | o_rx_clkout2 | The IP core asserts this signal to indicate that the IP received 10-bit code or data group in the current word boundary of o_rx_d or o_rx_c has a disparity error.
|
o_rx_errdetect[1:0] | 2 | o_rx_clkout2 | The IP core asserts this signal to indicate that it received 10-bit data group in the o_rx_d or o_rx_c has an 8b/10b code violation.
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