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Ixiasoft
2.1. Clock Signals
2.2. Reset Signals
2.3. TX MII Interface (64b/66b)
2.4. RX MII Interface (64b/66b)
2.5. Status Interface for 64b/66b Line Rate
2.6. TX Interface (8b/10b)
2.7. RX Interface (8b/10b)
2.8. Status Interface for 8b/10b Line Rate
2.9. Serial Interface
2.10. CPRI PHY Reconfiguration Interface
2.11. Datapath Avalon Memory-Mapped Interface
2.12. PMA Avalon Memory-Mapped Interface
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Ixiasoft
5.2. CDR Clock Output
Note: You can enable the CDR clock output only if the transceiver is placed at FGT transceiver Quad 3 or Quad 2 location.
When the Enable CDR Clock Output is turned on, the F-Tile CPRI PHY Multirate Intel® FPGA IP core generates with an extra interface link port (rx_cdr_divclk_link). Connect this port to the F-Tile Reference and System PLL Clocks Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP drives the CDR clock.
Figure 11. CDR Clock Output Connection
Line Rate (Gbps) | CDR Reference Clock (MHz) | CDR N Counter | CDR Out Clock (MHz) |
---|---|---|---|
24.33024 | 184.32 | 2 | 92.16 |
12.16512 | 184.32 | 6 | 30.72 |
10.1376 | 184.32 | 6 | 30.72 |
9.8304 | 153.6 | 6 | 25.6 |
6.144 | 153.6 | 6 | 25.6 |
4.9152 | 153.6 | 6 | 25.6 |
3.072 | 153.6 | 6 | 25.6 |
2.4576 | 153.6 | 6 | 25.6 |
1.2288 | 153.6 | 6 | 25.6 |