2.3.2.1. Clocking Scheme Components
Diagram Label | Description | ||||||||||
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TX PLL refclock 8 | TX PLL reference clock which can be any clock frequency that is divisible by transceiver for that data rate. This clock must be connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to SDI top module.
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TX PLL alt refclock | Second TX PLL reference clock can be any clock frequency that is divisible by transceiver for that data rate. This clock must be connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to SDI top module.
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RX CDR refclock 8 | Transceiver clock data recovery (CDR) reference clock, of any frequency divisible by the transceiver for that data rate. Only a single reference clock frequency which the recommendation is 148.5 MHz is required to support both integer and fractional frame rate. It must be a free running clock connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to SDI top module. |
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SysPLL refclock | F-Tile System PLL reference clock, of any frequency divisible by System PLL for that output frequency. It must be a free running clock connected from a dedicated transceiver reference clock pin to the input clock port of Reference and System PLL Clocks IP, before connecting the corresponding output port to SDI top module.
Note: For this demonstration, the System PLL clock output is set to the maximum supported frequency of 900 MHz. For your design, select a frequency that can support all the components that share the same PLL output. For example, set the output frequency to 891 MHz if no other component requires more than such frequency. This would allow 148.5 MHz as a refclock frequency option and enable you to share the same refclock pin as TX PLL refclock or RX CDR refclock to reduce the number of refclocks required.
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GPIO clock / RX coreclk / DR clocks | SDI RX core reference clock which must be a free running clock depending on the RX core clock Frequency parameter value. Intel recommends that you use the same clock source for rx/tx_rcfg_mgmt_clk as well as the clock to DR arbiter and DR IP. All generated design examples have this clock set to 148.5 MHz regardless of the GUI option because of the development kit's default limited clock frequency option. |
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TX PLL / RX CDR link clock | Output ports from Reference and System PLL Clocks IP. These clocks must be connected to the transceiver reference clock input of F-Tile Direct PHY IP. |
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System PLL output link clock | Output ports from Reference and System PLL Clocks IP. These clocks must be connected to the system PLL clock input of F-Tile Direct PHY IP.
The minimum System PLL output frequency for each SDI mode is given below:
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TX/RX transceiver clkout2 | Recovered clock from transceiver. For SD video standard:
For HD video standard:
For 3G/6G/12G video standard:
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TX/RX transceiver clkout | This is the div2 clock from System PLL output clock which the F-Tile PMA/FEC Direct PHY IP is operating in. This clock must be connected to a DCFIFO which serves as the interface between SDI II IP and the Direct PHY IP. | ||||||||||
AXIS clock | Clock for AXI4-Stream video. Clock frequency must be greater than 297 MHz. This clock is only available when you select AXIS-VVP Full active video data protocols. |