F-Tile SDI II Intel® FPGA IP Design Example User Guide

ID 710496
Date 7/08/2024
Public

1.5.1. Design Example Presets

The Parameter Editor includes four design example presets using different video standards that you can use to pre-configure the IP and target your device development kit and Nextera daughter card directly. Hover over a preset for its description.
Table 5.  Design Example Parameter Settings
Preset Parameter Settings
3G-SDI Serial Loopback
  • Under IP tab:
    • Video standard: 3G-SDI
    • Direction: Transmitter
    • Transmitter options: Insert payload ID enabled
  • Under Design Example tab:
    • Available Design Example: Serial loopback
    • Design Example Options: Dynamic TX clock switching disabled (can be enabled)
HD-SDI Serial Loopback
  • Under IP tab:
    • Video standard: HD-SDI
    • Direction: Transmitter
  • Under Design Example tab:
    • Available Design Example: Serial loopback
    • Design Example Options: Dynamic TX clock switching disabled (can be enabled)
Multi Rate Parallel Loopback with VCXO
  • Under IP tab:
    • Video standard: Multi Rate (up to 12G-SDI)
    • Direction: Receiver
    • Receiver options: CRC error output
  • Under Design Example tab:
    • Available Design Example: Parallel loopback with external VCXO
Triple Rate Parallel Loopback without VCXO
  • Under IP tab:
    • Video standard: Triple Rate (up to 3G-SDI)
    • Direction: Receiver
    • Receiver options: CRC error output
  • Under Design Example tab:
    • Available Design Example: Parallel loopback without external VCXO
Figure 12. Location of the Design Example Presets in the Parameter Editor