2.3.1. Design Components
The SDI II Intel FPGA IP core design examples require the following components.
Component | Description | ||||||||||
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SDI II |
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F-Tile PMA/FEC Direct PHY |
Note: For triple-rate or multi-rate mode design, F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP is used instead of the single rate version of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.
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SDI RX DR-F Mgmt |
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SDI TX DR-F Mgmt |
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PHY adapter | Adapter block which includes DCFIFO for converting the bit width of parallel data between transceiver and SDI core, and to transfer data between these two clock domains. |
Component | Description |
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Loopback FIFO | This module contains DCFIFO for transfer of video data between receiver clock domain and transmitter clock domain. This component is not available when you select AXIS-VVP Full active video data protocols. |
Reclock |
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Component | Description |
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Video Pattern Generator | Basic video pattern generator which can support SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. You can select static video with colorbar pattern or pathological pattern from this pattern generator. |
Pattern Gen Control PIO | Provides a memory-mapped interface for controlling the video pattern generator. |
JTAG to Avalon Master Bridge | Provides System Console host access to the Parallel I/O (PIO) IP in the design via the JTAG interface. |
Common Block | Description | ||||||||||
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Reference and System PLL Clocks | This IP connects the System PLL output clock as well as the TX PLL and RX CDR reference clock to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. System PLL clock output is always set to run at a higher clock frequency than the native PMA recovered clock.
Note: For this demonstration, the System PLL clock output is set to the maximum supported frequency of 900 MHz. For your design, select a frequency that can support all the components that share the same PLL output clock.
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F-Tile Dynamic Reconfiguration Suite IP (DR IP) | This IP is the main transceiver dynamic reconfiguration IP on F-Tile. To understand more about its operation, refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide. In the generated design example, this IP interfaces with a custom DR arbiter which arbitrates the reconfiguration requests from multiple SDI controllers. |
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DR Arbiter | This module serves as an arbiter to interface between F-Tile Dynamic Reconfiguration Suite IP (DR IP) and multiple SDI DR-F management controllers from different channels. The module prevents simultaneous reconfiguration requests to DR IP by multiple controllers by arbitrating the request in a round robin manner. | ||||||||||
System Reset | This module contains Reset Release Intel® FPGA IP to provide a known initialized state for system logic to begin operation. The module also includes a reset delay block to further delay the signal status from the IP for a safer operation. The reset delay block acts as a debouncer as well as for push button reset. For more information, refer to the Agilex™ 7 Reset Release Intel FPGA IP chapter in the Agilex™ 7 Configuration User Guide. |
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RX PHY Access | This module provides the capability for direct access to the PHY of the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP. It is essential in situations where the incoming video standard necessitates lock-to-reference clock (SD-Mode). In such scenarios, the module takes action to modify the PHY register settings, ensuring that the PHY operates in the accurate lock-to-reference clock mode. |