F-Tile SDI II Intel® FPGA IP Design Example User Guide

ID 710496
Date 7/08/2024
Public

2.1. Features

  1. LED status for early debugging stage with RX- or TX-only options.
  2. To use RX- or TX-only components, remove the irrelevant blocks from the simplex version serial loopback design as described in the following table.
    Table 6.  Features
    User Requirement Preserve Remove
    RX only
    • RX top
    • Reference and System PLL Clocks IP
    • DR IP & DR arbiter (if present)
    • Sys Reset
    TX Top
    TX only
    • TX top
    • Reference and System PLL Clocks IP
    • DR IP & DR arbiter (if present)
    • Sys Reset
    RX Top
Figure 13. Components Required for TX- or RX-Only Design on Agilex™ 7 Devices
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.