F-Tile SDI II Intel® FPGA IP Design Example User Guide

ID 710496
Date 7/08/2024
Public

2.3.2. Clocking Scheme

Figure 20. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note: When you select None active video data protocols, the DUTs are RX top and TX top.
Figure 21. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Note: When you select AXIS-VVP Full active video data protocols, Nios® V processor drives the control and status registers ( Avalon® memory-mapped) of both the SDI II TX and RX IP cores. The available DUTs are Nios® V Subsystem, RX PHY top and TX PHY top.
Figure 22. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note: When you select None active video data protocols, the DUT is Du top.
Figure 23. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Note:

When you select AXIS-VVP Full active video data protocols, Nios® V processor drives the control and status registers ( Avalon® memory-mapped) of both the SDI II TX and RX IP cores. The available DUTs are Nios® V Subsystem and Du PHY top.

Figure 24. Serial Loopback with Simplex Mode
Figure 25. Serial Loopback with Duplex Mode