F-Tile SDI II Intel® FPGA IP Design Example User Guide

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ID 710496
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide

2.6. Interface Signal

Table 17.  Top Level Signals
Signal Name Direction Width Description
On-board Oscillators
clk_a_12c_fgt_p_7 Input 1 156.25 MHz dedicated transceiver reference clock.
clk_a_12c_fgt_p_3 Input 1 148.5 MHz dedicated transceiver reference clock.
clk_3a_gpio_p_2 Input 1 148.5 MHz GPIO clock.
clk_a_12c_fgt_p_4 Input 1 Dedicated transceiver reference clock with default clock frequency of 153.6 MHz. You can change the clock frequency in Clock Control GUI to:
  • 148.35 MHz in a dynamic TX clock switching in serial loopback design to connect to the second TX PLL
  • 141 MHz in a parallel loopback without external VCXO design to connect to the TX PLL in fractional mode
User DIP Switches, Pushbuttons and LEDs
f_gpio_00 Input 1 Pushbutton to powerdown LMK03328 after switching the jumper settings.
fpga_resetn Input 1 Global reset.
fpga_sgpio_clk Input 1 SGPIO slave signals. These groups of signals connect to the MAX device to control the on-board LEDs and DIPSW.
fpga_sgpio_sync Input 1
fpga_sgpi Input 1
fgpa_sgpo Output 1
Nextera SDI FMC Daughter Card Pins on FMC Port A
clk_a_12c_fgt_p_1 Input 1 297/296.7 MHz dedicated transceiver reference clock from FMC port A.
fmc_a_rx_p_2/fmc_a_rx_n_2 Input 1 SDI RX serial data from FMC port A.
fmc_a_tx_p_0/fmc_a_tx_n_0 Output 1 SDI TX serial data from FMC port A.
fmc_a_la_p24 Output 1 Initialize LMH1983 on Nextera daughter card.
fmc_a_la_n24 Output 1 F sync signal to LMH1983 on Nextera daughter card.
fmc_a_la_p28 Output 1 V sync signal to LMH1983 on Nextera daughter card.
fmc_a_la_n28 Output 1 H sync signal to LMH1983 on Nextera daughter card.
fmc_a_la_p30 Output 1 Powerdown signal to LMK03328 on Nextera daughter card.
Table 18.  RX Top/ TX Top/ Du Top Parameters
Parameter Name Valid Value Default Value Description
TXPLL_REFCLK_PWRUP_FREQ 148.5, 148.35 148.5 Specifies the power up TX PLL reference clock frequency. This is to ensure that the correct profile number is taken for dynamic TX clocks switching.
MRPHY_TX_BASE_PROFILE <Must match with profile number set in assignment>

5

(mr & Txclk_sw),

3 (tr & Txclk_sw)

Defines the profile number that is set for TX transceiver.
MRPHY_RX_BASE_PROFILE <Must match with profile number set in assignment > 1 Defines the profile number that is set for RX transceiver.
RCFG_CLK_SDI_CORECLK_DIFF 0, 1 0 Enables if rx_core_refclk and rx_rcfg_mgmt_clk are using a different clock source.
NUM_STREAMS 1, 4 1 Defines the number of 20-bit data streams from SDI IP. For multirate mode, the value should be set to 4 while for other modes, the value should be set to 1.
Table 19.  RX Top/ TX Top/ Du Top SignalsThe DUTs are different if the parameter value is different. For more information about the DUT, refer to the figures in Clocking Scheme.
Signal Name Direction Width9 Description
Clocks
system_pll_clk Input 1 System PLL output clock. This port must be connected to the system PLL output port from Reference and System PLL Clocks IP.
rx_cdr_refclk Input 1 RX transceiver reference clock. This port must be connected to one of the output ports from Reference and System PLL Clocks IP.
rx_core_refclk 10 Input 1 SDI RX core clock. This clock must be a free-running clock and ranges between 100-156.25 MHz. Intel recommends that you share the same clock source as rx_rcfg_mgmt_clk if this is a triple-rate or multi-rate SDI RX.
tx_pll_refclk Input 1 TX PLL reference clock. This port must be connected to one of the output ports from Reference and System PLL Clocks IP.
tx_pll_refclk_alt Input 1 Secondary TX PLL reference clock. This port must be connected to one of the output ports from Reference and System PLL Clocks IP.
rx_rcfg_mgmt_clk Input 1 RX reconfiguration management clock. This clock must be a free-running clock and connected to the same clock as Dynamic Reconfiguration Suite (DR) IP.
tx_rcfg_mgmt_clk Input 1 TX reconfiguration management clock. This clock must be a free-running clock and connected to the same clock as Dynamic Reconfiguration Suite (DR) IP.
sdi_tx_pclk Input 1 SDI TX core parallel clock. This clock must be driven by one of the TX transceivers recovered parallel clocks. If there are multiple SDI TX which are getting video data from the same source, you may connect this.
rx_vid_clkout Output 1 RX transceiver recovered parallel clock for video data.
tx_vid_clkout Output 1 TX transceiver recovered parallel clock for video data.
Reset
sdi_tx_resetn Input 1 TX core reset signal.
tx_phy_resetn Input 1 PHY reset signal.
rx_resetn Input 1 RX core and PHY reset signal.
tx_rcfg_mgmt_resetn Input 1 TX reconfiguration reset signal.
rx_rcfg_mgmt_resetn Input 1 RX reconfiguration reset signal.
sdi_rx_rst_proto_out 10 Output 1 Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain.
Video Signal Interfaces (Interfacing with VIP Components)
rx_vid_data 10 Output 20*N Receiver parallel video data out.
rx_vid_datavalid 10 Output 1

Data valid signal generated from SDI RX core and has the following timing synchronous to rx_vid_clkout:

SD-SDI: 1H 4L 1H 5L

HD/3G/6G/12G-SDI: H

rx_vid_std 10 Output N Received video standard.
  • 3’b000: SD-SDI
  • 3’b001: HD-SDI
  • 3’b011: 3G-SDI Level A 10-bit Multiplex
  • 3’b010: 3G-SDI Level B 10-bit Multiplex
  • 3’b101: 6G-SDI 10-bit Multiplex Type 1
  • 3’b100: 6G-SDI 10-bit Multiplex Type 2
  • 3’b111: 12G-SDI 10-bit Multiplex Type 1
  • 3’b110: 12G-SDI 10-bit Multiplex Type 2
rx_vid_locked 10 Output 1 Frame locked indicating multiple frames with same timing have been spotted.
rx_vid_hsync 10 Output N Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.
rx_vid_vsync 10 Output   Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
rx_vid_f 10 Output N Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
rx_vid_trs 10 Output N Receiver output signal that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.
tx_vid_data 10 Input 20*N Transmitter parallel video data input.
tx_vid_datavalid 10 Input 1

Data valid for the transmitter parallel data. The timing (H:High, L:Low) must be as follows and synchronous to tx_pclk clock domain:

SD-SDI: 1H 4L 1H 5L

HD-SDI: 1H 1L (for triple/multi-rate)

H (for single-rate)

3G/6G/12G-SDI: H

tx_vid_std 10 Input 3 Indicates the desired transmit video standard.
  • 3’b000: SD-SDI
  • 3’b001: HD-SDI
  • 3’b011: 3G-SDI Level A 10-bit Multiplex
  • 3’b010: 3G-SDI Level B 10-bit Multiplex
  • 3’b101: 6G-SDI 10-bit Multiplex Type 1
  • 3’b100: 6G-SDI 10-bit Multiplex Type 2
  • 3’b111: 12G-SDI 10-bit Multiplex Type 1
  • 3’b110: 12G-SDI 10-bit Multiplex Type 2
tx_vid_trs 10 Input 1 Transmitter TRS input. For use in line number, CRC or payload ID insertion. Assert on first word of both EAV and SAV TRSs.
Other SDI Video Protocol Interfaces
sdi_tx_enable_crc 10 Input 1 Enable CRC insertion for all SDI video standards except SD-SDI.
sdi_tx_enable_ln 10 Input 1 Enable Line Number insertion for all SDI video standards except SD-SDI.
sdi_tx_ln 10 Input 11*N Line number to be inserted in the data stream when sdi_tx_enable_ln = 1.
sdi_tx_ln_b 10 Input 11*N Line number to be inserted in the data stream when sdi_tx_enable_ln = 1. For 3G level B and 6G/12G 10-bit Multiplex Type 2.
sdi_tx_vpid_overwrite 10 Input 1 Enable this signal to overwrite the existing payload ID embedded in the data stream.
sdi_tx_line_f0 10 Input 11*N Indicates the line number to be inserted with Payload ID.
sdi_tx_line_f1 10 Input 11*N
sdi_tx_vpid_byte1 10 Input 8*N Payload ID byte to be inserted in the payload ID field.
sdi_tx_vpid_byte2 10 Input 8*N
sdi_tx_vpid_byte3 10 Input 8*N
sdi_tx_vpid_byte4 10 Input 8*N
sdi_tx_vpid_byte1_b 10 Input 8*N
sdi_tx_vpid_byte2_b 10 Input 8*N
sdi_tx_vpid_byte3_b 10 Input 8*N
sdi_tx_vpid_byte4_b 10 Input 8*N
sdi_tx_datavalid 10 Output 1 Data valid signal generated from SDI TX core and has the following timing synchronous to tx_vid_clkout:
  • SD-SDI: 1H 4L 1H 5L
  • HD-SDI: 1H 1L (for triple/multi-rate)
  • H (for single rate)
  • 3G/6G/12G-SDI: H
sdi_rx_align_locked 10 Output 1 Alignment locked indicating a TRS has been spotted and word alignment performed.
sdi_rx_trs_locked 10 Output N TRS locked indicating six consecutive TRS with same timing have been spotted.
sdi_rx_clkout_is_ntsc_paln 10 Output 1

Indicates that the receiver is receiving video rate at integer or fractional frame rate.

  • 0 – Integer frame rate
  • 1 – Fractional frame rate
sdi_rx_format 10 Output 4*N Received video transport format. Refer to IP User Guide for the encoding value.
sdi_rx_ap 10 Output N Active picture interval timing signal. This signal is asserted when the active picture interval is active.
sdi_rx_eav 10 Output N Receiver output signal that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word.
sdi_rx_ln 10 Output 11*N Received line number output from protocol.
sdi_rx_ln_b 10 Output 11*N
sdi_rx_crc_error_c 10 Output N CRC error status signal from protocol.
sdi_rx_crc_error_y 10 Output N
sdi_rx_crc_error_c_b 10 Output N
sdi_rx_crc_error_y_b 10 Output N
sdi_rx_line_f0 10 Output 11*N Payload ID status signal from protocol.
sdi_rx_line_f1 10 Output 11*N
sdi_rx_vpid_byte1 10 Output 8*N
sdi_rx_vpid_byte2 10 Output 8*N
sdi_rx_vpid_byte3 10 Output 8*N
sdi_rx_vpid_byte4 10 Output 8*N
sdi_rx_vpid_checksum_error 10 Output N
sdi_rx_vpid_valid 10 Output N
sdi_rx_vpid_byte1_b 10 Output 8*N
sdi_rx_vpid_byte2_b 10 Output 8*N
sdi_rx_vpid_byte3_b 10 Output 8*N
sdi_rx_vpid_byte4_b 10 Output 8*N
sdi_rx_vpid_checksum_error_b 10 Output N
sdi_rx_vpid_valid_b 10 Output N
Transceiver Interfaces
tx_clk_sel_ntsc_paln 10 Input 1

Indicates which reference clock to be used for TX transceiver.

0 – 148.5 MHz clock

1 - 148.35 MHz clock
Note: Does not exist if TX clock dynamic switching feature is disabled.
gxb_rx_serial_data Input 1 RX transceiver serial data.
gxb_rx_serial_data_n Input 1 Differential pair of gxb_rx_serial_data.
gxb_tx_serial_data Output 1 TX transceiver serial data.
gxb_tx_serial_data_n Output 1 Differential pair of gxb_tx_serial_data.
gxb_rx_ready Output 1 Indicates that RX transceiver is out of reset and ready for data transfer.
gxb_tx_ready Output 1 Indicates that TX transceiver is out of reset and ready for data transfer.
gxb_tx_reset_ack Output 1 Indicates that TX transceiver is reset.
gxb_rx_reset_ack Output 1 Indicates that RX transceiver is reset.
tx_pll_locked Output 1 TX PLL lock status.
cdr_reconfig_busy Output 1 RX CDR reconfiguration status.
tx_reconfig_busy Output 1 TX PLL / transceiver reconfiguration status.
Transceiver Dynamic Reconfiguration Interfaces
dr_rx_new_cfg_applied Input 1 Reconfiguration interface signals from reconfig management block to DR arbiter.
dr_rx_new_cfg_applied_ack Output 1
dr_rx_avmm_write Output 1
dr_rx_avmm_read Output 1
dr_rx_avmm_address Output 10
dr_rx_avmm_writedata Output 32
dr_rx_avmm_readdata Input 32
dr_rx_avmm_readdata_valid Input 1
dr_rx_avmm_waitrequest Input 1
gxb_tx_reconfig_xcvr_avmm_write Input 1 Reconfiguration interface signals to Direct PHY IP’s AVMM interface for PLL’s fractional counter reconfiguration.
gxb_tx_reconfig_xcvr_avmm_read Input 1
gxb_tx_reconfig_xcvr_avmm_writedata Input 32
gxb_tx_reconfig_xcvr_avmm_address Input 18
gxb_tx_reconfig_xcvr_avmm_byteenable Input 4
gxb_tx_reconfig_xcvr_avmm_readdata Output 1
gxb_tx_reconfig_xcvr_avmm_readdatavalid Output 1
gxb_tx_reconfig_xcvr_avmm_waitrequest Output 1
Table 20.   Nios® V Subsystem Signals (Enable Active Video Data Protocols = AXIS-VVP Full)
Signal Name Direction Width Description
Clocks
cpu_clock_bridge_in_clk_clk Input 1 Clock for the Nios® V processor.
sdi_rx_mr_rx_coreclk_clk Input 1 SDI RX core clock. This clock must be a free-running clock and ranges between 100-156.25 MHz. Intel recommends that you share the same clock source as rx_rcfg_mgmt_clk if this is a Triple/Multi-Rate SDI RX.
sdi_rx_mr_xcvr_rxclk_clk Input 1 RX transceiver recovered parallel clock for video data.
sdi_tx_mr_tx_pclk_clk Input 1 TX transceiver recovered parallel clock for video data.
axi4s_clock_bridge_in_clk_clk Input 1 Clock for the AXI4-Stream video data.
Resets
cpu_reset_bridge_in_reset_reset Input 1 Reset for the Nios® V processor.
axi4s_reset_bridge_in_reset_reset Input 1 Reset for the AXI4-Stream video data.
SDI <-> PHY / Reclock Interfaces
sdi_rx_mr_rx_datain_rx_parallel_data Input 20*N RX transceiver recovered parallel data.
sdi_rx_mr_gxb_ltr_fgt_rx_set_locktoref Output 1 Set-to-locktoref control for transceiver.
sdi_rx_mr_rx_ready_rx_ready Input 1 When asserted, indicates that the RX transceiver is ready.
sdi_rx_mr_rx_xcvr_reset_ack_rx_reset_ack Input 1 Status signal from RX transceiver indicating that the RX is fully in reset.
sdi_rx_mr_trig_rst_ctrl_reset Output 1 Reset output to the transceiver reset controller to reset the transceiver.
sdi_rx_mr_rx_rst_proto_out_export Output 1 Reset signal generated by the SDI RX.
sdi_rx_mr_rx_format_export Output 4 Received video transport format.
sdi_rx_mr_rx_align_locked_export Output 1 Alignment locked indicating a TRS has been spotted and word alignment performed.
sdi_rx_mr_rx_trs_locked_export Output N TRS locked indicating six consecutive TRSs with same timing has been spotted.
sdi_rx_mr_rx_frame_locked_export Output 1 Frame locked indicating multiple frames with same timing has been spotted.
sdi_rx_mr_rx_std_export Output 3 Received SDI video standard.
sdi_rx_mr_rx_h_export Output N Horizontal blanking interval timing signal. The RX asserts this signal when the horizontal blanking interval is active.
sdi_rx_mr_rx_f_export Output N Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
sdi_rx_mr_rx_v_export Output N Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
sdi_rx_mr_rx_vpid_checksum_error_export Output N Payload ID status signal from protocol.
sdi_rx_mr_rx_vpid_checksum_error_b_export Output N Payload ID status signal from protocol.
sdi_rx_mr_rx_clkout_is_ntsc_paln_export Output 1 Indicates that the RX is receiving video rate at NTSC (1/1.001) or PAL (1) rate.
sdi_rx_mr_rx_sdi_start_reconfig_export Output 1 Request from the RX to start the dynamic reconfiguration.
sdi_rx_mr_rx_sdi_reconfig_done_export Input 1 Indicates back to the RX that the dynamic reconfiguration has finished.
sdi_tx_mr_tx_dataout_valid_export Output 1 Data valid generated by the TX. The timing (H:High, L:Low) as follows:
  • SD-SDI: 1H 4L 1H 5L
  • HD-SDI: 1H 1L
  • 3G-SDI: H
  • 6G-SDI: H
  • 12G-SDI: H
sdi_tx_mr_tx_dataout_tx_parallel_data Output 20*N Parallel data from the TX.
Table 21.  Loopback Top Parameter
Parameter Name Valid Value Default Value Description
XCVR_RCFG_ADDR_WIDTH 11 18 18 Defines the reconfiguration Avalon® memory-mapped interface address bus width.
XCVR_RCFG_DATA_WIDTH 11 32 32 Defines the reconfiguration Avalon® memory-mapped interface data bus width.
FGT_LANE_NUM 11 0-3 0

Defines the lane number where the TX PLL to be reconfigured is located.

TX_PLL_MODE 11 Fast, Medium, Slow Medium

Defines the TX PLL band.

You may refer to Direct PHY IP GUI to get its value when you enable TX FGT PLL fractional mode.

NUM_STREAMS 1, 4 1 Defines the number of 20-bit data streams from SDI IP. For multirate mode, the value should be set to 4 while for other modes, the value should be set to 1.
VIDEO_STANDARD hd, 3g, tr, mr tr Defines the current video standard mode of SDI IP core that this loopback module is interacting with.
Table 22.  Loopback Top Signals
Signal Name Direction Width Description
Clocks
sdi_tx_clkout Input 1 TX transceiver recovered parallel clock for video data.
sdi_rx_clkout Input 1 RX transceiver recovered parallel clock for video data.
sdi_reclk_sysclk Input 1 Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk.
Resets
sdi_rx_rst_proto Input 1 Reset signal from RX SDI core to indicate that the protocol is currently held in reset.
sdi_reclk_rst Input 1 Reset signal to reclock module (without external VCXO solution).
gxb_tx_ready 12 Input 1 Used as a reset signal to internal FIFO to indicate that the TX is ready to receive.
SDI Related Signals
sdi_rx_dataout 12 Input 20*N Receiver recovered parallel video data.
sdi_rx_dataout_valid 12 Input 1 Data valid signal generated from SDI RX core.
sdi_rx_std Input 3 Received video standard from SDI RX core.
sdi_rx_trs 12 Input N Receiver output signal from SDI core that indicates current word is TRS.
sdi_rx_trs_locked Input N TRS locked status signal from SDI RX core.
sdi_rx_frame_locked Input 1 Frame locked status signal from SDI RX core.
sdi_tx_dataout_valid 12 Input 1 Data valid signal generated from SDI TX core.
sdi_rx_h Input 1 Horizontal blanking interval timing signal extracted from SDI Rx core.
sdi_rx_format Input 4 Received video transport format.
sdi_rx_clkout_is_ntsc_paln Input 1 Indication from SDI Rx core that the receiver is receiving video rate at integer or fractional frame rate.
sdi_tx_datain 12 Output 20*N Parallel video data input to SDI TX core.
sdi_tx_datain_valid 12 Output 1 Data valid for the transmitter parallel data to SDI TX core.
sdi_tx_trs 12 Output 1 Transmitter TRS input to indicate that the current word is a TRS to SDI TX core.
sdi_tx_std 12 Output 3 Indicates the desired transmit video standard to SDI TX core.
TX PHY Reconfiguration Signals
pll_locked Input 1 PLL lock status signal.
pll_reconfig_readdata Input 32 Reconfiguration interface signals to fPLL AVMM interface.
pll_reconfig_readdatavalid Input 1
pll_reconfig_waitrequest Input 1
pll_reconfig_write Output 1
pll_reconfig_read Output 1
pll_reconfig_byteenable Output 4
pll_reconfig_writedata Output 32
pll_reconfig_address Output 18
Note: N=4 for multirate, otherwise N=1.
Table 23.  Reclock Module Parameter
Parameter Name Valid Value Default Value Description
XCVR_RCFG_ADDR_WIDTH 11 18 18 Defines the reconfiguration Avalon® memory-mapped interface address bus width.
XCVR_RCFG_DATA_WIDTH 11 32 32 Defines the reconfiguration Avalon® memory-mapped interface data bus width.
FGT_LANE_NUM 11 0-3 0

Defines the lane number where the TX PLL to be reconfigured is located.

TX_PLL_MODE 11 Fast, Medium, Slow Medium Defines the TX PLL band. You may refer to Direct PHY IP GUI to get its value when you enable TX FGT PLL fractional mode.
VIDEO_STANDARD hd, 3g, tr, mr tr

Defines the current video standard mode of SDI IP core that this loopback module is interacting with.

Table 24.  Reclock Module
Signal Name Direction Width Description
Clocks
tx_clkout Input 1 TX transceiver recovered parallel clock for video data.
rx_clkout Input 1 RX transceiver recovered parallel clock for video data.
sysclk Input 1 Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk.
Resets
rx_rst_proto Input 1 Reset signal from RX SDI core to indicate that the protocol is currently held in reset.
reset Input 1 Reset signal to reclock module (without external VCXO solution).
SDI Related Signals
rx_std Input 3 Received video standard from SDI RX core.
rx_trs_locked Input N TRS locked status signal from SDI RX core.
rx_frame_locked Input 1 Frame locked status signal from SDI RX core.
rx_h Input 1 Horizontal blanking interval timing signal extracted from SDI Rx core.
rx_format Input 4 Received video transport format.
rx_clkout_is_nts c_paln Input 1 Indication from SDI Rx core that the receiver is receiving video rate at integer or fractional frame rate.
TX PHY Reconfiguration Signals
pll_locked Input 1 PLL lock status signal.
read_data Input 32 Reconfiguration interface signals to fPLL AVMM interface.
read_data_valid Input 1
waitrequest_signal Input 1
write_signal Output 1
read_signal Output 1
byte_enable_signal Output 4
write_data Output 32
address_signal Output 18
Note: N=4 for multirate, otherwise N=1.
Table 25.  DR Arbiter Parameters
Parameter Name Valid Value Default Value Description
NUM_DR_HOST 1-32 1 Defines the number of reconfiguration hosts that are interacting with DR IP.
PIPELINE_ENA 0,1 0 Enables pipeline registers on the avmm to interface between reconfiguration hosts and DR IP. You may set this to ‘1’ if you are seeing any timing issue within this module, else may leave it as ‘0’ for better resource utilization.
AVMM_ADDRESS_WIDTH 10 10 Defines the avmm address port width interfacing with DR IP. The set value should be matching with the corresponding port size on DR IP.
AVMM_DATA_WIDTH 32 32 Defines the avmm writedata/readdata port width interfacing with DR IP. The set value should be matching with the corresponding port size on DR IP.
Table 26.  DR Arbiter Signals
Signal Name Direction Width Description
clk Input 1 Reconfiguration clock. This clock should be sharing the same clock as i_csr_clk on DR IP.
reset Input 1 Reset signal. This reset should be sharing the same reset as DR IP.
reconfig_en Input 1*NUM_DR_HOST Reconfiguration enable signal. The port size follows the value on NUM_DR_HOST parameter.
rcfg_mgmt_write_ch Input 1*NUM_DR_HOST Reconfiguration AVMM interfaces from individual SDI DR-F mgmt.
rcfg_mgmt_read_ch Input 1*NUM_DR_HOST
rcfg_mgmt_address_ch Input 10*NUM_DR_HOST
rcfg_mgmt_writedata_ch Input 32*NUM_DR_HOST
rcfg_mgmt_readdata_ch Output 32*NUM_DR_HOST
rcfg_mgmt_waitrequest_ch Output 1*NUM_DR_HOST
rcfg_mgmt_readdata_valid_ch Output 1*NUM_DR_HOST
rcfg_mgmt_new_cfg_applied_ch Output 1*NUM_DR_HOST Indicates that the reconfiguration operation is done to the respective host according to the bit arrangement in reconfig_en port.
rcfg_mgmt_new_cfg_applied_ack_ch Input 1*NUM_DR_HOST Acknowledge signal to the DR IP on the reconfiguration done from each respective SDI reconfiguration host.
dr_avmm_write Output 1 Reconfiguration AVMM interfaces to DR IP.
dr_avmm_read Output 1
dr_avmm_address Output

10
dr_avmm_writedata Output 32
dr_avmm_readdata Input 32
dr_avmm_readdata_valid Input 1
dr_avmm_waitrequest Input 1
dr_new_cfg_applied Input 1 Indicates that the reconfiguration operation is done from DR IP.
dr_new_cfg_applied_ack Output 1 Acknowledge signal to the DR IP on the reconfiguration done.
Table 27.  Video Pattern Generator Parameters
Parameter Name Valid Value Default Value Description
OUTW_MULTP 1, 4 1 Defines the output ports width. Select 4 for a multirate design, otherwise select 1.
SD_BIT_WIDTH 10, 20 10 Defines the generated SD interface bit width. This value must match with the SD interface bit width parameter of SDI II TX core in the same design.
TEST_GEN_ANC 0, 1 0 Enable to generate ancillary data packet in output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled.
TEST_GEN_VPID 0, 1 0 Enable to generate payload ID packet in output streams. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled.
Table 28.  Video Pattern Generator Signals
Signal Name Direction Width Description
clk Input 1 Clock signal. This clock must be connected to tx_vid_clkout clock signal from TX/Du top.
rst Input 1 Reset signal. This reset signal should be synchronized with tx_vid_clkout clock signal from TX/Du top.
bar_100_75n Input 1 Enable this signal to generate 100% colorbar pattern, else 75% colorbar pattern.
enable Input 1 This signal acts as a data valid signal to this module. This signal should be connected to sdi_tx_datavalid signal from TX/Du top.
patho Input 1 Enable this signal to generate pathological pattern.
blank Input 1 Enable this signal to generate black signal.
no_color Input 1 Enable this signal to generate bar with no color.
sgmt_frame Input 1 Enable this signal to generate payload ID for segmented frame video format when generating 1080i50 or 1080i60 video.
tx_std Input 3 Indicates the desired transmit video standard. This input signal must match with tx_vid_std on TX/Du top.
tx_format Input 4 Indicates the desired transmit video format.
dl_mapping Input 1 Enable this signal to generate data streams with dual-link mapping. This is only applicable for HD dual link or 3G Level B Dual link video standard.
ntsc_paln Input 1 Enable this signal to generate payload ID for fractional frame rate video format, else the module generates integer frame rate version.
dout Output 20*N Data output signal to be connected to tx_vid_data input signal on TX/Du top.
dout_valid Output 1 Data valid output signal to be connected to tx_vid_datavalid input signal on TX/Du top.
trs Output 1 TRS output signal to be connected to tx_vid_trs input signal on TX/Du top.
ln Output 11*N Line number output signal to be connected to sdi_tx_ln input signal on TX/Du top.
dout_b Output 20 Data output signal for link B (HD dual-link).
dout_valid_b Output 1 Data valid output signal for link B (HD dual-link).
trs_b Output 1 TRS output signal for link B (HD dual-link).
ln_b Output 11*N Line number output signal to be connected to sdi_tx_ln_b input signal on TX/Du top.
vpid_byte1 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte1 input signal on TX/Du top.
vpid_byte2 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte2 input signal on TX/Du top.
vpid_byte3 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte3 input signal on TX/Du top.
vpid_byte4 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte4 input signal on TX/Du top.
vpid_byte1_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte1_b input signal on TX/Du top.
vpid_byte2_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte2_b input signal on TX/Du top.
vpid_byte3_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte3_b input signal on TX/Du top.
vpid_byte4_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte4_b input signal on TX/Du top.
line_f0 Output 11*N Line number output signal to be inserted with Payload ID. This signal must be connected to sdi_tx_line_f0 input signal on TX/Du top.
line_f1 Output 11*N Line number output signal to be inserted with Payload ID. This signal must be connected to sdi_tx_line_f1 input signal on TX/Du top.
Table 29.  Pattern Generator Control Module Signals
Signal Name Direction Width Description
avmm_clk_in_clk Input 1 Clock signal to AVMM interface.
tx_clkout_in_clk Input 1 Clock signal to Parallel I/O (PIO) IP. This clock must share the same clock as video pattern generator.
avmm_clk_reset_n Input 1 Reset signal to AVMM interface.
pattgen_rst_reset_in0 Input 1 Input reset signals to a reset synchronizer which synchronize the reset to tx_clkout_in_clk clock domain.
pattgen_rst_reset_in1 Input 1
pattgen_rst_reset_out Input 1 Output reset from reset synchronizer. This reset is synchronized to tx_clkout_in_clk clock domain and connected to video pattern generator’s input reset.
pattgen_ctrl_pio_out_port Output 12 Output control signal from PIO to control video pattern generator.
Table 30.  Sys Reset Module Signals
Signal Name Direction Width Description
clk Input 1 Clock signal to reset delay module.
async_rstn Input 1 Global reset.
out_reset Output 1 Reset signal. Indicates user reset and device has not finished its initialization stage after a programmable delay which is determined by CNTR_BITS parameter.
Note: CNTR_BITS parameter determines the bit width of the delay counter. Default value is set to 16.
9 N = 4 for multirate, otherwise N = 1.
10 This signal is not supported when you select AXIS-VVP Full active video data protocol.
11 This parameter is only used in parallel loopback without external VCXO design.
12 This signal is not available when Enable active video data protocols = AXIS-VVP Full.
Level Two Title