Visible to Intel only — GUID: cbf1637222479919
Ixiasoft
2.3. Functional Description
The SDI II Intel® FPGA IP core design example supports the following simplex and duplex transceiver modes:
- Parallel loopback with simplex mode
- Parallel loopback with duplex mode
- Serial loopback with simplex mode
- Serial loopback with duplex mode
Figure 14. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 15. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Figure 16. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 17. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Figure 18. Serial Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note:
- Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
- Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.
Figure 19. Serial Loopback with Duplex Mode IP Core (Enable active video data protocols = None)