F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 12/22/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.5.2. Serial loopback

To run the hardware test, connect the transmitter output pin to receiver input pin directly. To validate whether RX is locked to the signal and receive the video data correctly, the on-board LEDs are used to display the RX status.

You may also connect an SDI signal analyzer to the transmitter output pin to view the generated image.

Figure 29. Intel Agilex I-Series SoC Development Kit User LEDs
Table 15.  On-board LED Functions
LEDs Functions
D2, D4, D6 Indicate the receiver video standard.
D8 Shows the slower version of TX transceiver parallel clock.
D7 Shows the slower version of RX transceiver parallel clock.
D1 Illuminates when align_locked signal is asserted.
D3 Illuminates when trs_locked signal is asserted
D5 Illuminates when frame_locked signal is asserted.
Table 16.  D3-D5 LED status and its video standard on Agilex I-series SoC Development Kit
D2, D4, D6 Video standard
000 SD
001 HD
010 3G Level B 10-bit Multiplex
011 3G Level A 10-bit Multiplex
100 6G 10-bit Multiplex Type 2
101 6G 10-bit Multiplex Type 1
110 12G 10-bit Multiplex Type 2
111 12G 10-bit Multiplex Type 1
Level Two Title