F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 12/22/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.3.1. Design Components

The SDI II Intel FPGA IP core design examples require the following components.

Table 7.  Device Under Test (DUT) ComponentsThe DUTs are RX top, TX top, and Du Top. The DUTs are different if the parameter value is different. For more information about the DUT, refer to the figures in Clocking Scheme.
Component Description
SDI II
  • TX
    • The IP core receives video data from top level and encodes the necessary information, for example line number, CRC or payload ID into the data streams.
  • RX
    • The IP core receives parallel data from Transceiver Native PHY and performs the necessary decoding, such as descrambling, realigning the data, and extracting the necessary information.
    • The output data from these blocks connects to the SDI F-tile PHY adapter module before passing it to F-tile PMA/FEC Direct PHY Intel® FPGA IP.
When you select AXIS-VVP Full active video data protocols, these IPs instantiate as part of Nios® II Subsystem. The RX PHY top, TX PHY top, and Du PHY top are composed of PHY related IPs only.
F-tile PMA/FEC Direct PHY
  • TX
    • Hard transceiver block which receives parallel data from SDI core and serializes the data before transmitting it.
  • RX
    • Hard transceiver block to receive serial data from an external video source.
    • The rx/tx_xcvr_reset_ack output signal from this block should be connected to the SDI RX/TX DR-F mgmt module to indicate that the transceiver is in reset.
    • The PHY runs in System PLL clocking mode and system clock output always runs at a higher clock frequency than the native PMA recovered clock.
SDI mode Minimum System PLL Output Frequency
HD-SDI single rate 150 MHz
3G-SDI single rate 300 MHz
Triple-rate SDI (up to 3G-SDI) 300 MHz
Multi-rate SDI (up to 12G-SDI) 600 MHz
Note: For triple-rate or multi-rate mode design, F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP is used instead of the single rate version of the F-tile PMA/FEC Direct PHY Intel® FPGA IP.
SDI RX DR-F Mgmt
  • RX transceiver reconfiguration management to reconfigure F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP to receive different data rates from SD-SDI up to 12G-SDI.
  • Rx_xcvr_reset_ack from transceiver must be connected to this block to indicate transceiver’s status.
SDI TX DR-F Mgmt
  • TX transceiver reconfiguration management to reconfigure F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP to change the TX clock dynamically for switching between integer or fractional frame rate.
  • Tx_xcvr_reset_ack from transceiver and PLLs are required to indicate transceiver’s status in Dynamic TX clocks switching design.
PHY adapter Adapter block which includes DCFIFO for converting the bit width of parallel data between transceiver and SDI core, and to transfer data between these two clock domains.
Table 8.  Loopback Top Components
Component Description
Loopback FIFO This module contains DCFIFO for transfer of video data between receiver clock domain and transmitter clock domain. This component is not available when you select AXIS-VVP Full active video data protocols.
Reclock
  • This module is required for the Parallel loopback without external VCXO design for comparing the phase between receiver parallel clock and transmitter parallel clocks.
  • The output interfaces of this block are connected to the reconfiguration Avalon® memory-mapped interface interfaces of TX PHY reconfiguration transceiver. If there is any difference in term of frequency between these clock domains, this module generates the Avalon® memory-mapped interface transactions to reconfigure TX PLL so that both the clock frequencies are as close as possible.
Table 9.  Video Pattern Generator Components
Component Description
Video Pattern Generator Basic video pattern generator which can support SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. You can select static video with colorbar pattern or pathological pattern from this pattern generator.
Pattern Gen Control PIO Provides a memory-mapped interface for controlling the video pattern generator.
JTAG to Avalon Master Bridge Provides System Console host access to the Parallel I/O (PIO) IP in the design via the JTAG interface.
Table 10.  Common Blocks at Top Level
Common Block Description
Reference and System PLL Clocks

This IP connects the System PLL output clock as well as the TX PLL and RX CDR reference clock to the F-tile PMA/FEC Direct PHY Intel® FPGA IP.

System PLL clock output is always set to run at a higher clock frequency than the native PMA recovered clock.

SDI mode Minimum System PLL output frequency
HD-SDI single rate 150 MHz
3G-SDI single rate 300 MHz
Triple-rate SDI (up to 3G-SDI) 300 MHz
Multi-rate SDI (up to 12G-SDI) 600 MHz
Note: For this demonstration, the System PLL clock output is set to the maximum supported frequency of 900 MHz. For your design, select a frequency that can support all the components that share the same PLL output clock.
F-tile Dynamic Reconfiguration Suite IP (DR IP)
  • This IP is the main transceiver dynamic reconfiguration IP on F-tile. To understand more about its operation, refer to F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide.
  • In the generated design example, this IP interfaces with a custom DR arbiter which arbitrates the reconfiguration requests from multiple SDI controllers.
DR Arbiter This module serves as an arbiter to interface between F-tile Dynamic Reconfiguration Suite IP (DR IP) and multiple SDI DR-F management controllers from different channels. The module prevents simultaneous reconfiguration requests to DR IP by multiple controllers by arbitrating the request in a round robin manner.
Device Initialization This module contains Reset Release Intel FPGA IP to provide a known initialized state for system logic to begin operation. The module also includes a reset delay block to further delay the signal status from the IP for a safer operation. For more information, refer to the Intel Agilex Reset Release Intel FPGA IP chapter in the Intel Agilex Configuration User Guide.
Related Information
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