F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 12/22/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.3. Functional Description

The SDI II Intel® FPGA IP core design example supports the following simplex and duplex transceiver mode:.
  • Parallel loopback with simplex mode
  • Parallel loopback with duplex mode
  • Serial loopback with simplex mode
  • Serial loopback with duplex mode
Figure 14. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 15. Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Figure 16. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 17. Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full)
Figure 18. Serial Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.
Figure 19. Serial Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.

Section Content
Design Components
Clocking Scheme

Level Two Title