F-Tile SDI II FPGA IP Design Example User Guide

ID 710496
Date 12/22/2022
Public

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2.5.1. Parallel loopback

To run the hardware test, connect an SDI video generator to the receiver input pin. To validate whether RX is locked to the signal and receive the video data correctly, the on-board LEDs are used to display the RX status.

After verifying that RX is working fine, connect an SDI signal analyzer to the transmitter output. The same image which is being generated from the source should be displayed on the signal analyzer.

For design examples with Enable active video data protocols set to AXIS-VVP Full, the following table shows the supported formats:

Table 14.  Supported Video Formats for Design Examples with AXIS-VVP Full Enabled
Video Standard Video Format Frame Rate
SD 486i 59.94
SD 576i 50
HD 720p 60
HD 1080i 60

HD

3G (A / B-DL)

6G Mode 2

1080p 30, 60
6G Mode 2 2K (2048x1080) 30, 60
6G Mode 1/12G Mode 1 2160p 30, 60
6G Mode 1/12G Mode 1 4K (4096x2160) 30, 60