F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.3
IP Version 19.3.0
The SDI II Intel® FPGA IP design example for Intel® Agilex™ F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
When you generate the design example, the IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: The hardware support for the SDI II Intel FPGA IP design example for Intel® Agilex™ F-tile devices is in preliminary status.
Figure 1. Development Stages

Section Content
Directory Structure
Generating the Design
Simulating the Design
Compiling and Testing the Design in Hardware
Design Example Parameters

Level Two Title