F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

1.5. Design Example Parameters

Table 4.  Parameters available in Design Example tab
Parameter Value Description
Select Design
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback

Select available design example to be generated.

  • Parallel loopback with external VCXO: Parallel loopback design with an external VCXO to synchronize the clock between RX and TX.
    Note: In the Intel® Agilex™ device family, the FVH sync output signals from RX core is not accurate enough to clock the external VCXO in SD-SDI mode for genlocking purpose. As a workaround, Intel recommends to use an external sync separator to generate this signal to the external VCXO. Alternatively, you can use parallel loopback without VCXO design example.
  • Parallel loopback without external VCXO: Parallel loopback design utilizes internal PLL on Intel® FPGA IP to synchronize the clock between RX and TX. The TX PLL is operating in fractional mode with a 141 MHz as its reference clock frequency.
  • Serial loopback: An internal video pattern generator generates along with TX and transmits to RX. This design allows simple demonstration when you do not have a video source available.
    Note: Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol in the IP tab.
Dynamic TX clock Switching
  • Off
  • TX PLL reference clock switching

Turns on this option to allow dynamic switching between 1 and 1/1.001 data rates. Tx reference clock switching requires two reference clocks for TX PLL.

Note: TX PLL reference clock switching is only available when you select Serial Loopback design.
Simulation On / Off Turns on this option to generate necessary files for simulation testbench.
Note: Simulation is not supported when you select AXIS-VVP Full active video data protocol in the IP tab.
Synthesis On

Turns on this option to generate necessary files for Intel® Quartus® Prime compilation and hardware demo.

This option is greyed out and set to always Enabled. This is because synthesis files are still required to run Support-Logic Generation stage in Intel® Quartus® Prime to generate the transceiver tile’s files which are essential to run simulation as well.

Generate File Format
  • Verilog
  • VHDL
 Select the HDL format for generated design example fileset. Note that the HDL format only affects the generated top level IP files. All the other files, for example testbenches and top level files for hardware demo are in Verilog.
Select Daughter card
  • Nextera VIDIO 12G-SDI FMC card

Select the daughter card for the targeted design example. This option is greyed out as only Nextera VIDIO 12G-SDI FMC card is supported in this design example.

Select Board
  • No Development Kit
  • Agilex I-Series SOC Development Kit
  • Custom Development Kit

Select the board for the targeted design example.

  • No Development Kit: This option excludes hardware aspects for the design example. All the pin assignments are set to virtual pins.
  • Agilex I-Series SOC Development Kit: This option automatically selects the project’s target device to match the device on this development kit. You may change the target device with the “Change Target Device” parameter below if your board revision has a different grade of the default targeted device. All the pins assignment has been set accordingly to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with Intel FPGA device. You may need to set the pin assignment on your own.
Change Target Device On / Off

Turn on this option and select the preferred device variant for the development kit.
Related Information
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