2.6. Interface Signal
Signal Name | Direction | Width | Description |
---|---|---|---|
On-board Oscillators | |||
clk_a_12c_fgt_p_7 | Input | 1 | 156.25 MHz dedicated transceiver reference clock. |
clk_a_12c_fgt_p_3 | Input | 1 | 148.5 MHz dedicated transceiver reference clock. |
clk_3a_gpio_p_2 | Input | 1 | 148.5 MHz GPIO clock. |
clk_a_12c_fgt_p_4 | Input | 1 | Dedicated transceiver reference clock with default clock frequency of 153.6 MHz. You can change the clock frequency in Clock Control GUI to:
|
User DIP switches, pushbuttons and LEDs | |||
f_gpio_00 | Input | 1 | Pushbutton to powerdown LMK03328 after switching the jumper settings. |
fpga_resetn | Input | 1 | Global reset |
fpga_sgpio_clk | Input | 1 | SGPIO slave signals. These groups of signals connect to the MAX device to control the on-board LEDs and DIPSW. |
fpga_sgpio_sync | Input | 1 | |
fpga_sgpi | Input | 1 | |
fgpa_sgpo | Output | 1 | |
Nextera SDI FMC daughter card pins on FMC port A | |||
clk_a_12c_fgt_p_1 | Input | 1 | 297/296.7 MHz dedicated transceiver reference clock from FMC port A. |
fmc_a_rx_p_2/fmc_a_rx_n_2 | Input | 1 | SDI RX serial data from FMC port A. |
fmc_a_tx_p_0/fmc_a_tx_n_0 | Output | 1 | SDI TX serial data from FMC port A. |
fmc_a_la_p24 | Output | 1 | Initialize LMH1983 on Nextera daughter card. |
fmc_a_la_n24 | Output | 1 | F sync signal to LMH1983 on Nextera daughter card. |
fmc_a_la_p28 | Output | 1 | V sync signal to LMH1983 on Nextera daughter card. |
fmc_a_la_n28 | Output | 1 | H sync signal to LMH1983 on Nextera daughter card. |
fmc_a_la_p30 | Output | 1 | Powerdown signal to LMK03328 on Nextera daughter card. |
Parameter name | Valid value | Default Value | Description |
---|---|---|---|
TXPLL_REFCLK_PWRUP_FREQ | 148.5, 148.35 | 148.5 | Specifies the power up TX PLL reference clock frequency. This is to ensure that the correct profile number is taken for dynamic TX clocks switching. |
DR_TX_CLK148M5_PROFILE | <Must match with profile number set in assignment> | 5 (du_top), 1 (tx_top) |
Define the profile number that is set for TX PLL with reference clock frequency of 148.5 MHz for this instance. |
DR_TX_CLK148M35_PROFILE | <Must match with profile number set in assignment > | 6 (du_top), 2 (tx_top) |
Define the profile number that is set for TX PLL with reference clock frequency of 148.35 MHz for this instance. |
DR_RX_12G_PROFILE | <Must match with profile number set in assignment > | 1 | Define the profile number that is set for RX transceiver with 12G-SDI configuration for this instance. |
DR_RX_6G_PROFILE | <Must match with profile number set in assignment > | 2 | Define the profile number that is set for RX transceiver with 6G-SDI configuration for this instance. |
DR_RX_3GSD_PROFILE | <Must match with profile number set in assignment > | 3 | Define the profile number that is set for RX transceiver with 3G-SDI/SD-SDI configuration for this instance. |
DR_RX_HD_PROFILE | <Must match with profile number set in assignment > | 4 | Define the profile number that is set for RX transceiver with HD-SDI configuration for this instance. |
NUM_STREAMS | 1, 4 | 1 | Define the number of 20-bit data streams from SDI IP. For multirate mode, the value should be set to 4 while for other modes, the value should be set to 1. |
Signal Name | Direction | Width 9 | Description |
---|---|---|---|
Clocks | |||
system_pll_clk | Input | 1 | System PLL output clock. This port must be connected to the system PLL output port from Reference and System PLL Clocks IP. |
rx_cdr_refclk | Input | 1 | RX transceiver reference clock. This port must be connected to one of the output ports from Reference and System PLL Clocks IP. |
rx_core_refclk | Input | 1 | SDI RX core clock. This clock must be a free-running clock and ranges between 100-156.25 MHz. Intel recommends you to share the same clock source as rx_rcfg_mgmt_clk if this is a triple-rate or multi-rate SDI Rx. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
tx_pll_refclk | Input | 1 | TX PLL reference clock. This port must be connected to one of the output ports from Reference and System PLL Clocks IP. |
tx_pll_refclk_alt | Input | 1 | Secondary TX PLL reference clock. This port must be connected to one of the output ports from Reference and System PLL Clocks IP. |
rx_rcfg_mgmt_clk | Input | 1 | Rx reconfiguration management clock. This clock must be a free-running clock and connected to the same clock as Dynamic Reconfiguration Suite (DR) IP. |
tx_rcfg_mgmt_clk | Input | 1 | TX reconfiguration management clock. This clock must be a free-running clock and connected to the same clock as Dynamic Reconfiguration Suite (DR) IP. |
sdi_tx_pclk | Input | 1 | SDI TX core parallel clock. This clock must be driven by one of the TX transceivers recovered parallel clocks. If there are multiple SDI TX which are getting video data from the same source, you may connect this |
rx_vid_clkout | Output | 1 | RX transceiver recovered parallel clock for video data. |
tx_vid_clkout | Output | 1 | TX transceiver recovered parallel clock for video data. |
Reset | |||
tx_resetn | Input | 1 | TX core and PHY reset signal. |
rx_resetn | Input | 1 | RX core and PHY reset signal |
tx_rcfg_mgmt_resetn | Input | 1 | TX reconfiguration reset signal. |
rx_rcfg_mgmt_resetn | Input | 1 | Rx reconfiguration reset signal. |
sdi_rx_rst_proto_out | Output | 1 | Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
Video signal interfaces (Interfacing with VIP components) | |||
rx_vid_data | Output | 20*N | Receiver parallel video data out. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
rx_vid_datavalid | Output | 1 | Data valid signal generated from SDI RX core and has the following timing synchronous to rx_vid_clkout:
SD-SDI: 1H 4L 1H 5L HD/3G/6G/12G-SDI: H This signal is not supported when you select AXIS-VVP Full active video data protocol. |
rx_vid_std | Output | N | Received video standard.
This signal is not supported when you select AXIS-VVP Full active video data protocol. |
rx_vid_locked | Output | 1 | Frame locked indicating multiple frames with same timing have been spotted. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
rx_vid_hsync | Output | N | Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
rx_vid_vsync | Output | Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
|
rx_vid_f | Output | N | Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
rx_vid_trs | Output | N | Receiver output signal that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
tx_vid_data | Input | 20*N | Transmitter parallel video data input. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
tx_vid_datavalid | Input | 1 | Data valid for the transmitter parallel data. The timing (H:High, L:Low) must be as follows and synchronous to tx_pclk clock domain:
SD-SDI: 1H 4L 1H 5L HD-SDI: 1H 1L (for triple/multi-rate) H (for single-rate) 3G/6G/12G-SDI: H This signal is not supported when you select AXIS-VVP Full active video data protocol. |
tx_vid_std | Input | 3 | Indicates the desired transmit video standard.
This signal is not supported when you select AXIS-VVP Full active video data protocol. |
tx_vid_trs | Input | 1 | Transmitter TRS input. For use in line number, CRC or payload ID insertion. Assert on first word of both EAV and SAV TRSs. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
Other SDI video protocol interfaces | |||
sdi_tx_enable_crc | Input | 1 | Enable CRC insertion for all SDI video standards except SD-SDI. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_enable_ln | Input | 1 | Enable Line Number insertion for all SDI video standards except SD-SDI. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_ln | Input | 11*N | Line number to be inserted in the data stream when sdi_tx_enable_ln = 1. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_ln_b | Input | 11*N | Line number to be inserted in the data stream when sdi_tx_enable_ln = 1. For 3G level B and 6G/12G 10-bit Multiplex Type 2. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_vpid_overwrite | Input | 1 | Enable this signal to overwrite the existing payload ID embedded in the data stream. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_line_f0 | Input | 11*N | Indicates the line number to be inserted with Payload ID. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_line_f1 | Input | 11*N | |
sdi_tx_vpid_byte1 | Input | 8*N | Payload ID byte to be inserted in the payload ID field. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_tx_vpid_byte2 | Input | 8*N | |
sdi_tx_vpid_byte3 | Input | 8*N | |
sdi_tx_vpid_byte4 | Input | 8*N | |
sdi_tx_vpid_byte1_b | Input | 8*N | |
sdi_tx_vpid_byte2_b | Input | 8*N | |
sdi_tx_vpid_byte3_b | Input | 8*N | |
sdi_tx_vpid_byte4_b | Input | 8*N | |
sdi_tx_datavalid | Output | 1 | Data valid signal generated from SDI TX core and has the following timing synchronous to tx_vid_clkout:
This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_align_locked | Output | 1 | Alignment locked indicating a TRS has been spotted and word alignment performed. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_trs_locked | Output | N | TRS locked indicating six consecutive TRS with same timing have been spotted. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_clkout_is_ntsc_paln | Output | 1 | Indicates that the receiver is receiving video rate at integer or fractional frame rate.
This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_format | Output | 4*N | Received video transport format. Refer to IP User Guide for the encoding value. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_ap | Output | N | Active picture interval timing signal. This signal is asserted when the active picture interval is active. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_eav | Output | N | Receiver output signal that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_ln | Output | 11*N | Received line number output from protocol. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_ln_b | Output | 11*N | |
sdi_rx_crc_error_c | Output | N | CRC error status signal from protocol. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_crc_error_y | Output | N | |
sdi_rx_crc_error_c_b | Output | N | |
sdi_rx_crc_error_y_b | Output | N | |
sdi_rx_line_f0 | Output | 11*N | Payload ID status signal from protocol. This signal is not supported when you select AXIS-VVP Full active video data protocol. |
sdi_rx_line_f1 | Output | 11*N | |
sdi_rx_vpid_byte1 | Output | 8*N | |
sdi_rx_vpid_byte2 | Output | 8*N | |
sdi_rx_vpid_byte3 | Output | 8*N | |
sdi_rx_vpid_byte4 | Output | 8*N | |
sdi_rx_vpid_checksum_error | Output | N | |
sdi_rx_vpid_valid | Output | N | |
sdi_rx_vpid_byte1_b | Output | 8*N | |
sdi_rx_vpid_byte2_b | Output | 8*N | |
sdi_rx_vpid_byte3_b | Output | 8*N | |
sdi_rx_vpid_byte4_b | Output | 8*N | |
sdi_rx_vpid_checksum_error_b | Output | N | |
sdi_rx_vpid_valid_b | Output | N | |
Transceiver Interfaces | |||
tx_clk_sel_ntsc_paln | Input | 1 | Indicates which reference clock to be used for TX transceiver. 0 – 148.5 MHz clock
1 - 148.35 MHz clock
Note: Do not exists if TX clock dynamic switching feature is disabled.
This signal is not supported when you select AXIS-VVP Full active video data protocol. |
gxb_rx_serial_data | Input | 1 | RX transceiver serial data |
gxb_rx_serial_data_n | Input | 1 | Differential pair of gxb_rx_serial_data. |
gxb_tx_serial_data | Output | 1 | TX transceiver serial data |
gxb_tx_serial_data_n | Output | 1 | Differential pair of gxb_tx_serial_data. |
gxb_rx_ready | Output | 1 | Indicates that RX transceiver is out of reset and ready for data transfer. |
gxb_tx_ready | Output | 1 | Indicates that TX transceiver is out of reset and ready for data transfer. |
gxb_tx_reset_ack | Output | 1 | Indicates that TX transceiver is reset. |
gxb_rx_reset_ack | Output | 1 | Indicates that RX transceiver is reset. |
tx_pll_locked | Output | 1 | TX PLL lock status |
cdr_reconfig_busy | Output | 1 | RX CDR reconfiguration status |
tx_reconfig_busy | Output | 1 | TX PLL / transceiver reconfiguration status |
Transceiver Dynamic Reconfiguration Interfaces | |||
dr_rx_new_cfg_applied | Input | 1 | Reconfiguration interface signals from reconfig management block to DR arbiter. |
dr_rx_new_cfg_applied_ack | Output | 1 | |
dr_rx_avmm_write | Output | 1 | |
dr_rx_avmm_read | Output | 1 | |
dr_rx_avmm_address | Output | 10 | |
dr_rx_avmm_writedata | Output | 32 | |
dr_rx_avmm_readdata | Input | 32 | |
dr_rx_avmm_readdata_valid | Input | 1 | |
dr_rx_avmm_waitrequest | Input | 1 | |
gxb_tx_reconfig_xcvr_avmm_write | Input | 1 | Reconfiguration interface signals to Direct PHY IP’s AVMM interface for PLL’s fractional counter reconfiguration. |
gxb_tx_reconfig_xcvr_avmm_read | Input | 1 | |
gxb_tx_reconfig_xcvr_avmm_writedata | Input | 32 | |
gxb_tx_reconfig_xcvr_avmm_address | Input | 18 | |
gxb_tx_reconfig_xcvr_avmm_byteenable | Input | 4 | |
gxb_tx_reconfig_xcvr_avmm_readdata | Output | 1 | |
gxb_tx_reconfig_xcvr_avmm_readdatavalid | Output | 1 | |
gxb_tx_reconfig_xcvr_avmm_waitrequest | Output | 1 |
Signal Name | Direction | Width | Description |
---|---|---|---|
Clocks | |||
cpu_clock_bridge_in_clk_clk | Input | 1 | Clock for the Nios II processor. |
sdi_rx_mr_rx_coreclk_clk | Input | 1 | SDI Rx core clock. This clock must be a free-running clock and ranges between 100-156.25 MHz. It is recommended to share the same clock source as rx_rcfg_mgmt_clk if this is a Triple/Multi-Rate SDI Rx. |
sdi_rx_mr_xcvr_rxclk_clk | Input | 1 | Rx transceiver recovered parallel clock for video data. |
sdi_tx_mr_tx_pclk_clk | Input | 1 | Tx transceiver recovered parallel clock for video data. |
axi4s_clock_bridge_in_clk_clk | Input | 1 | Clock for the AXI4-Stream video data. |
Resets | |||
cpu_reset_bridge_in_reset_reset | Input | 1 | Reset for the Nios II processor. |
axi4s_reset_bridge_in_reset_reset | Input | 1 | Reset for the AXI4-Stream video data. |
SDI <-> PHY / Reclock Interfaces | |||
sdi_rx_mr_rx_datain_rx_parallel_data | Input | 20*N | Rx transceiver recovered parallel data. |
sdi_rx_mr_gxb_ltr_fgt_rx_set_locktoref | Output | 1 | Set-to-locktoref control for transceiver. |
sdi_rx_mr_rx_ready_rx_ready | Input | 1 | When asserted, indicates that the Rx transceiver is ready. |
sdi_rx_mr_rx_xcvr_reset_ack_rx_reset_ack | Input | 1 | Status signal from Rx transceiver indicating that the Rx is fully in reset. |
sdi_rx_mr_trig_rst_ctrl_reset | Output | 1 | Reset output to the transceiver reset controller to reset the transceiver. |
sdi_rx_mr_rx_rst_proto_out_export | Output | 1 | Reset signal generated by the SDI Rx. |
sdi_rx_mr_rx_format_export | Output | 4 | Received video transport format. |
sdi_rx_mr_rx_align_locked_export | Output | 1 | Alignment locked indicating a TRS has been spotted and word alignment performed. |
sdi_rx_mr_rx_trs_locked_export | Output | N | TRS locked indicating six consecutive TRSs with same timing has been spotted. |
sdi_rx_mr_rx_frame_locked_export | Output | 1 | Frame locked indicating multiple frames with same timing has been spotted. |
sdi_rx_mr_rx_std_export | Output | 3 | Received SDI video standard. |
sdi_rx_mr_rx_h_export | Output | N | Horizontal blanking interval timing signal. The Rx asserts this signal when the horizontal blanking interval is active. |
sdi_rx_mr_rx_clkout_is_ntsc_paln_export | Output | 1 | Indicates that the Rx is receiving video rate at NTSC (1/1.001) or PAL (1) rate. |
sdi_rx_mr_rx_sdi_start_reconfig_export | Output | 1 | Request from the Rx to start the dynamic reconfiguration. |
sdi_rx_mr_rx_sdi_reconfig_done_export | Input | 1 | Indicates back to the Rx that the dynamic reconfiguration has finished. |
sdi_tx_mr_tx_dataout_valid_export | Output | 1 | Data valid generated by the Tx. The timing (H:High, L:Low) as follows:
|
sdi_tx_mr_tx_dataout_tx_parallel_data | Output | 20*N | Parallel data from the Tx. |
Parameter name | Valid value | Default Value | Description |
---|---|---|---|
XCVR_RCFG_ADDR_WIDTH | 18 | 18 | Define the reconfiguration Avalon® memory-mapped interface address bus width. This parameter is only used in parallel loopback without external VCXO design. |
XCVR_RCFG_DATA_WIDTH | 32 | 32 | Define the reconfiguration Avalon® memory-mapped interface data bus width. This parameter is only used in parallel loopback without external VCXO design. |
FGT_LANE_NUM | 0-3 | 0 | Define the lane number where the TX PLL to be reconfigured is located. This parameter is only used in parallel loopback without external VCXO design. |
TX_PLL_MODE | Fast, Medium, Slow | Medium | Define the TX PLL band. You may refer to Direct PHY IP GUI to get its value when you enable TX FGT PLL fractional mode. This parameter is only used in parallel loopback without external VCXO design. |
NUM_STREAMS | 1, 4 | 1 | Define the number of 20-bit data streams from SDI IP. For multirate mode, the value should be set to 4 while for other modes, the value should be set to 1. |
VIDEO_STANDARD | hd, 3g, tr, mr | tr | Define the current video standard mode of SDI IP core that this loopback module is interacting with. |
Signal Name | Direction | Width | Description |
---|---|---|---|
Clocks | |||
sdi_tx_clkout | Input | 1 | TX transceiver recovered parallel clock for video data. |
sdi_rx_clkout | Input | 1 | RX transceiver recovered parallel clock for video data. |
sdi_reclk_sysclk | Input | 1 | Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk. |
Resets | |||
sdi_rx_rst_proto | Input | 1 | Reset signal from RX SDI core to indicate that the protocol is currently held in reset. |
sdi_reclk_rst | Input | 1 | Reset signal to reclock module (without external VCXO solution). |
gxb_tx_ready | Input | 1 | Used as a reset signal to internal FIFO to indicate that the TX is ready to receive. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
SDI related signals | |||
sdi_rx_dataout | Input | 20*N | Receiver recovered parallel video data. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_rx_dataout_valid | Input | 1 | Data valid signal generated from SDI RX core. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_rx_std | Input | 3 | Received video standard from SDI RX core |
sdi_rx_trs | Input | N | Receiver output signal from SDI core that indicates current word is TRS. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_rx_trs_locked | Input | N | TRS locked status signal from SDI RX core |
sdi_rx_frame_locked | Input | 1 | Frame locked status signal from SDI RX core |
sdi_tx_dataout_valid | Input | 1 | Data valid signal generated from SDI TX core. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_rx_h | Input | 1 | Horizontal blanking interval timing signal extracted from SDI Rx core |
sdi_rx_format | Input | 4 | Received video transport format |
sdi_rx_clkout_is_ntsc_paln | Input | 1 | Indication from SDI Rx core that the receiver is receiving video rate at integer or fractional frame rate. |
sdi_tx_datain | Output | 20*N | Parallel video data input to SDI TX core. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_tx_datain_valid | Output | 1 | Data valid for the transmitter parallel data to SDI TX core. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_tx_trs | Output | 1 | Transmitter TRS input to indicate that the current word is a TRS to SDI TX core. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
sdi_tx_std | Output | 3 | Indicates the desired transmit video standard to SDI TX core. This signal is not available when Enable active video data protocols = AXIS-VVP Full. |
Tx PHY reconfiguration signals | |||
pll_locked | Input | 1 | PLL lock status signal |
pll_reconfig_readdata | Input | 32 | Reconfiguration interface signals to fPLL AVMM interface |
pll_reconfig_readdatavalid | Input | 1 | |
pll_reconfig_waitrequest | Input | 1 | |
pll_reconfig_write | Output | 1 | |
pll_reconfig_read | Output | 1 | |
pll_reconfig_byteenable | Output | 4 | |
pll_reconfig_writedata | Output | 32 | |
pll_reconfig_address | Output | 18 |
Parameter name | Valid value | Default Value | Description |
---|---|---|---|
XCVR_RCFG_ADDR_WIDTH | 18 | 18 | Define the reconfiguration Avalon® memory-mapped interface address bus width. This parameter is only used in parallel loopback without external VCXO design. |
XCVR_RCFG_DATA_WIDTH | 32 | 32 | Define the reconfiguration Avalon® memory-mapped interface data bus width. This parameter is only used in parallel loopback without external VCXO design. |
FGT_LANE_NUM | 0-3 | 0 | Define the lane number where the TX PLL to be reconfigured is located. This parameter is only used in parallel loopback without external VCXO design. |
TX_PLL_MODE | Fast, Medium, Slow | Medium | Define the TX PLL band. You may refer to Direct PHY IP GUI to get its value when you enable TX FGT PLL fractional mode. This parameter is only used in parallel loopback without external VCXO design. |
VIDEO_STANDARD | hd, 3g, tr, mr | tr | Define the current video standard mode of SDI IP core that this loopback module is interacting with. |
Signal Name | Direction | Width | Description |
---|---|---|---|
Clocks | |||
tx_clkout | Input | 1 | TX transceiver recovered parallel clock for video data. |
rx_clkout | Input | 1 | RX transceiver recovered parallel clock for video data. |
sysclk | Input | 1 | Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk. |
Resets | |||
rx_rst_proto | Input | 1 | Reset signal from RX SDI core to indicate that the protocol is currently held in reset. |
reset | Input | 1 | Reset signal to reclock module (without external VCXO solution). |
SDI related signals | |||
rx_std | Input | 3 | Received video standard from SDI RX core |
rx_trs_locked | Input | N | TRS locked status signal from SDI RX core |
rx_frame_locked | Input | 1 | Frame locked status signal from SDI RX core |
rx_h | Input | 1 | Horizontal blanking interval timing signal extracted from SDI Rx core |
rx_format | Input | 4 | Received video transport format |
rx_clkout_is_nts c_paln | Input | 1 | Indication from SDI Rx core that the receiver is receiving video rate at integer or fractional frame rate |
Tx PHY reconfiguration signals | |||
pll_locked | Input | 1 | PLL lock status signal |
read_data | Input | 32 | Reconfiguration interface signals to fPLL AVMM interface |
read_data_valid | Input | 1 | |
waitrequest_signal | Input | 1 | |
write_signal | Output | 1 | |
read_signal | Output | 1 | |
byte_enable_signal | Output | 4 | |
write_data | Output | 32 | |
address_signal | Output | 18 |
Parameter name | Valid value | Default Value | Description |
---|---|---|---|
NUM_DR_HOST | 1-32 | 1 | Define the number of reconfiguration hosts that are interacting with DR IP. |
PIPELINE_ENA | 0,1 | 0 | Enable to allow pipeline registers on the avmm interfaces between reconfiguration hosts and DR IP. You may set this to ‘1’ if you are seeing any timing issue within this module, else may leave it as ‘0’ for better resource utilization. |
AVMM_ADDRESS_WIDTH | 10 | 10 | Define the avmm address port width interfacing with DR IP. The set value should be matching with the corresponding port size on DR IP. |
AVMM_DATA_WIDTH | 32 | 32 | Define the avmm writedata/readdata port width interfacing with DR IP. The set value should be matching with the corresponding port size on DR IP. |
Signal names | Direction | Width | Description |
---|---|---|---|
clk | Input | 1 | Reconfiguration clock. This clock should be sharing the same clock as i_csr_clk on DR IP. |
reset | Input | 1 | Reset signal. This reset should be sharing the same reset as DR IP. |
reconfig_en | Input | 1*NUM_DR_HOST | Reconfiguration enable signal. The port size follows the value on NUM_DR_HOST parameter. |
rcfg_mgmt_write_ch | Input | 1*NUM_DR_HOST | Reconfiguration AVMM interfaces from individual SDI DR-F mgmt. |
rcfg_mgmt_read_ch | Input | 1*NUM_DR_HOST | |
rcfg_mgmt_address_ch | Input | 10*NUM_DR_HOST | |
rcfg_mgmt_writedata_ch | Input | 32*NUM_DR_HOST | |
rcfg_mgmt_readdata_ch | Output | 32*NUM_DR_HOST | |
rcfg_mgmt_waitrequest_ch | Output | 1*NUM_DR_HOST | |
rcfg_mgmt_readdata_valid_ch | Output | 1*NUM_DR_HOST | |
rcfg_mgmt_new_cfg_applied_ch | Output | 1*NUM_DR_HOST | Indicates that the reconfiguration operation is done to the respective host according to the bit arrangement in reconfig_en port. |
rcfg_mgmt_new_cfg_applied_ack_ch | Input | 1*NUM_DR_HOST | Acknowledge signal to the DR IP on the reconfiguration done from each respective SDI reconfiguration host. |
dr_avmm_write | Output | 1 | Reconfiguration AVMM interfaces to DR IP. |
dr_avmm_read | Output | 1 | |
dr_avmm_address | Output | 10 |
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dr_avmm_writedata | Output | 32 | |
dr_avmm_readdata | Input | 32 | |
dr_avmm_readdata_valid | Input | 1 | |
dr_avmm_waitrequest | Input | 1 | |
dr_new_cfg_applied | Input | 1 | Indicates that the reconfiguration operation is done from DR IP. |
dr_new_cfg_applied_ack | Output | 1 | Acknowledge signal to the DR IP on the reconfiguration done |
Parameter name | Valid value | Default Value | Description |
---|---|---|---|
OUTW_MULTP | 1, 4 | 1 | Define the output ports width. Select 4 for a multirate design, otherwise select 1. |
SD_BIT_WIDTH | 10, 20 | 10 | Define the generated SD interface bit width. This value must match with the SD interface bit width parameter of SDI II TX core in the same design. |
TEST_GEN_ANC | 0, 1 | 0 | Enable to generate ancillary data packet in output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled. |
TEST_GEN_VPID | 0, 1 | 0 | Enable to generate payload ID packet in output streams. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled. |
Signal names | Direction | Width | Description |
---|---|---|---|
clk | Input | 1 | Clock signal. This clock must be connected to tx_vid_clkout clock signal from TX/Du top. |
rst | Input | 1 | Reset signal. This reset signal should be synchronized with tx_vid_clkout clock signal from TX/Du top. |
bar_100_75n | Input | 1 | Enable this signal to generate 100% colorbar pattern, else 75% colorbar pattern. |
enable | Input | 1 | This signal acts as a data valid signal to this module. This signal should be connected to sdi_tx_datavalid signal from TX/Du top. |
patho | Input | 1 | Enable this signal to generate pathological pattern. |
blank | Input | 1 | Enable this signal to generate black signal. |
no_color | Input | 1 | Enable this signal to generate bar with no color. |
sgmt_frame | Input | 1 | Enable this signal to generate payload ID for segmented frame video format when generating 1080i50 or 1080i60 video. |
tx_std | Input | 3 | Indicates the desired transmit video standard. This input signal must match with tx_vid_std on TX/Du top. |
tx_format | Input | 4 | Indicates the desired transmit video format. |
dl_mapping | Input | 1 | Enable this signal to generate data streams with dual-link mapping. This is only applicable for HD dual link or 3G Level B Dual link video standard. |
ntsc_paln | Input | 1 | Enable this signal to generate payload ID for fractional frame rate video format, else the module generates integer frame rate version. |
dout | Output | 20*N | Data output signal to be connected to tx_vid_data input signal on TX/Du top. |
dout_valid | Output | 1 | Data valid output signal to be connected to tx_vid_datavalid input signal on TX/Du top. |
trs | Output | 1 | TRS output signal to be connected to tx_vid_trs input signal on TX/Du top. |
ln | Output | 11*N | Line number output signal to be connected to sdi_tx_ln input signal on TX/Du top. |
dout_b | Output | 20 | Data output signal for link B (HD dual-link). |
dout_valid_b | Output | 1 | Data valid output signal for link B (HD dual-link). |
trs_b | Output | 1 | TRS output signal for link B (HD dual-link). |
ln_b | Output | 11*N | Line number output signal to be connected to sdi_tx_ln_b input signal on TX/Du top. |
vpid_byte1 | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte1 input signal on TX/Du top. |
vpid_byte2 | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte2 input signal on TX/Du top. |
vpid_byte3 | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte3 input signal on TX/Du top. |
vpid_byte4 | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte4 input signal on TX/Du top. |
vpid_byte1_b | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte1_b input signal on TX/Du top. |
vpid_byte2_b | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte2_b input signal on TX/Du top. |
vpid_byte3_b | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte3_b input signal on TX/Du top. |
vpid_byte4_b | Output | 8*N | Payload ID output signal to be connected to sdi_tx_vpid_byte4_b input signal on TX/Du top. |
line_f0 | Output | 11*N | Line number output signal to be inserted with Payload ID. This signal must be connected to sdi_tx_line_f0 input signal on TX/Du top. |
line_f1 | Output | 11*N | Line number output signal to be inserted with Payload ID. This signal must be connected to sdi_tx_line_f1 input signal on TX/Du top. |
Signal name | Direction | Width | Description |
---|---|---|---|
avmm_clk_in_clk | Input | 1 | Clock signal to AVMM interface. |
tx_clkout_in_clk | Input | 1 | Clock signal to Parallel I/O (PIO) IP. This clock must share the same clock as video pattern generator. |
avmm_clk_reset_n | Input | 1 | Reset signal to AVMM interface. |
pattgen_rst_reset_in0 | Input | 1 | Input reset signals to a reset synchronizer which synchronize the reset to tx_clkout_in_clk clock domain. |
pattgen_rst_reset_in1 | Input | 1 | |
pattgen_rst_reset_out | Input | 1 | Output reset from reset synchronizer. This reset is synchronized to tx_clkout_in_clk clock domain and connected to video pattern generator’s input reset. |
pattgen_ctrl_pio_out_port | Output | 12 | Output control signal from PIO to control video pattern generator. |
Signal name | Direction | Width | Description |
---|---|---|---|
clk | Input | 1 | Clock signal to reset delay module |
init_done | Output | 1 | Indicates device has finished its initialization stage after a programmable delay which is determined by CNTR_BITS parameter. Note: CNTR_BITS parameter determines the bit width of the delay counter. Default value is set to 16. |