F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

1.1. Directory Structure

The directories contain the generated files for the design example. The hardware support for the SDI II Intel® FPGA IP design example for Intel® Agilex™ F-tile devices is in preliminary status.
Figure 2. Directory Structure for the Design Example
Table 1.  Other Generated Files in RTL Folder
Folders Files
vid_pattgen /sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/pattgen_ctrl.qsys
<qsys generated folder>
loopback /loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
/pfd/clock_crossing.v 1
/pfd/pfd.sdc 1
/pfd/pfd.v 1
/reclock/pid_controller.sv 1
/reclock /rcfg_pll_frac.sv 1
/reclock/sdi_reclock.sv 1
du /du_<vid_std>_phy_top.sv 4
/du_<vid_std>_top.sv 5
sdi_<vid_std>_du_sys.qsys 5
/sdi_rx_dr_f.sv (optional) 2
/sdi_tx_dr_f.sv (optional) 3
<qsys generated folder>
rx /rx_<vid_std>_phy_top.sv 4
rx <vid_std>_phy.ip 4
/rx_<vid_std>_top.sv 5
/sdi_<vid_std>_rx_sys.qsys 5
/sdi_rx_dr_f.sv (optional) 2
<ip/qsys generated folder>
tx tx_<vid_std>_phy_top.sv 4
tx_<vid_std>_phy.ip 4
/tx_<vid_std>_top.sv 5
/sdi_<vid_std>_tx_sys.qsys
/sdi_tx_dr_f.sv (optional) 3
<ip/qsys generated folder>
phy_adapter /sdi_ftile_phy_adapter.sv
/sdi_ftile_phy_adapter.sdc
/rxdata_3ghd_fifo.ip
/rxdata_6g_fifo.ip (optional) 6
/rxdata_12g_fifo.ip (optional) 6
txdata_fifo.ip
<ip generated folder>
Table 2.   Other Generated Files in Simulation Folder
Folders Files
mentor /mentor.do
synopsys /vcs/filelist.f
/vcs/vcs_sim.sh
/vcsmx/vcsmx_sim.sh
testbench /tb_top.sv
/rx_checker/sdi_ii_tb_rx_checker.v
/rx_checker/tb_data_compare.v
/rx_checker/tb_dual_link_sync.v
/rx_checker/tb_fifo_line_test.v
/rx_checker/tb_frame_locked_test.sv
/rx_checker/tb_ln_check.v
/rx_checker/tb_rxsample_test.v
/rx_checker/tb_trs_locked_test.sv
/rx_checker/tb_txpll_test.sv
/rx_checker/tb_vpid_check.v
/tb_control/sdi_ii_tb_control.v
/tb_control/tb_clk_rst.v
/tb_control/tb_data_delay.v
/tb_control/tb_serial_delay.sv
/tb_control/tb_tasks.v
/tb_checker/sdi_ii_tb_tx_checker.v
/tb_checker/tb_serial_check_counter.v
/tb_checker/tb_serial_descrambler.v
/tb_checker/tb_tx_clkout_check.v
/vid_pattgen/sdi_ii_colorbar_gen.v
/vid_pattgen/sdi_ii_ed_vid_pattgen.v 7
/vid_pattgen/sdi_ii_makeframe.v 7
/vid_pattgen/sdi_ii_patho_gen.v 7
xcelium /xcelium_sim.sh
1 For parallel loopback without external VCXO design
2 Only in Intel® Agilex™ Triple/Multi rate mode Design Example
3 Only in Intel® Agilex™ Dynamic Tx clock switching enabled Design Example
4 For Intel® Agilex™ AXIS-VVP FULL Design Example only
5 For non AXIS-VVP FULL Design Example only
6 Only in Intel® Agilex™ Multi-rate mode Design Example
7 For parallel loopback design
Level Two Title