F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-Tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-Tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

2.7. Clocking Scheme

The clocking scheme illustrates the clock domains in the HDMI Intel® FPGA IP design example.
Figure 23. HDMI 2.1 Design Example Clocking Scheme
Table 15.  Clocking Scheme Signals
Clock Signal Name in Design Description
Management Clock

mgmt_clk

A free running 100 MHz clock for these components:
  • IOPLL (Video Clock)
  • CPU
  • I2C Master
  • HDMI TX Core
  • RX-TX Link
I2C Clock i2c_clk

A 100 MHz clock input that clocks I2C slave, output buffers, SCDC registers, and link training process in the HDMI RX core, and EDID RAM.

Video Clock tx_vid_clk/rx_vid_clk

Video clock to TX and RX core. The clock runs at a fixed frequency of 225 MHz.
TX/RX FRL Clock tx_frl_clk/rx_frl_clk

FRL clock to for TX and RX core.
RX PHY Clock Out 1 rx_sysclk_div2

System clock output clock to clock data from the transceiver. The frequency is system clock frequency/2. System clock frequency needs to be higher than the fastest PMA clock frequency, with the valid bit from the transceiver parallel data bus indicating the validity of data.

For this HDMI design example, the rx_sysclk_div2 is 450MHz as the System PLL output frequency is 900MHz.

RX PHY Clock Out 2 rx_clk

Clock out recovered from the transceiver, and the frequency varies depending on the data rate and transceiver width.

RX transceiver clock out frequency = Transceiver data rate/ Transceiver width

For this HDMI design example, the RX transceiver clock out from channel 1 clocks the RX transceiver core input (rx_coreclkin) and FRL IOPLL (pll_frl_rx) reference clock

TX PHY Clock Out 1 tx_sysclk_div2

System clock output clock to clock data from the transceiver. The frequency is system clock frequency/2. System clock frequency needs to be higher than the fastest PMA clock frequency, with the valid bit from the transceiver parallel data bus indicating the validity of data.

For this HDMI design example, the tx_sysclk_div2 is 450 MHz as the System PLL output frequency is 900 MHz.
TX PHY Clock Out 2 tx_clk

Parallel clock generated from system PLL, and the frequency varies depending on the data rate and transceiver width.

TX transceiver clock out frequency = Transceiver data rate/ Transceiver width

For this HDMI design example, the TX transceiver clock out from channel 1 clocks the TX transceiver core input (rx_coreclkin) and FRL IOPLL (pll_frl_tx) reference clock.

Transceiver TMDS Reference Clock fgt_refclk_148p5 Reference clock to the F-tile Reference and System PLL Clock IP for TMDS mode
System PLL Reference Clock fgt_refclk_100 Reference clock to the System PLL block. The clock only supports 100 MHz frequency.
System PLL Clock systempll_clk Reference clock to the TX and RX Transceiver System PLL Clock. The clock frequency is 100 MHz.
Transceiver Reference Clock refclk_fgt Reference clock to the TX PLL and RX CDR.
TX Cadence Clock tx_cadence_clk Clock for the tx_cadence_slow_clk in the TX transceiver to generate the tx_cadence. Since there is a conversion of the data width from 40 bits from TX core to 64 bits in TX transceiver, the tx_cadence_slow_clk needs to be supplied with a clock derived from transceiver output clock with the frequency 5/8*Tx transceiver clock frequency.
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