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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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3.6.3. Initialize RX Path
Perform necessary initialization on the RX path.
- Check if the external HDMI sink supports FRL.
- EDID passthrough from the external HDMI sink to Intel HDMI RX or configure the EDID RAM based on the predefined EDID in the software according to different FRL rate.
The selection between EDID passthrough (LOOPBACK_MODE=1) or predefined EDID (LOOPBACK_MODE=0) is based on the LOOPBACK_MODE definition in the global.h.
Note: You need to run with EDID passthrough (LOOPBACK_MODE=1) when running on TMDS mode.
Refer to the Initialize RX Path Flowchart figure for more details.