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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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2.11.3. Clock Frequency Measurement
Use this feature to check the frequency for the different clocks.
- In the hdmi_rx_top and hdmi_tx_top files, uncomment //`define DEBUG_EN 1.
- Add the refclock_measure signal from each mr_rate_detect instance to the Signal Tap Logic Analyzer to get the clock frequency of each clock (in 10 ms duration).
- Compile the design with Signal Tap Logic Analyzer.
- Program the SOF file and run the Signal Tap Logic Analyzer.
Module | mr_rate_detect Instance | Clock to be Measured |
---|---|---|
hdmi_rx_top | rx_pll_tmds | RX CDR reference clock 0 |
rx_clk0_freq | RX transceiver clock out from channel 0 | |
rx_vid_clk_freq | RX video clock | |
rx_frl_clk_freq | RX FRL clock | |
rx_hsync_freq | Hsync frequency of the received video frame | |
hdmi_tx_top | tx_clk0_freq | TX transceiver clock out from channel 0 |
vid_clk_freq | TX video clock | |
frl_clk_freq | TX FRL clock | |
tx_hsync_freq | Hsync frequency of the video frame to be transmitted |