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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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3.1. Design Features
Setting the Enable Active Video Protocol to AXIS-VVP gives two design variants:
- HDMI 2.1 RX-TX Direct Retransmit without video frame buffer
- Fixed 225 MHz for TX and RX video clock (vid_clk) for the direct retransmit of the design
- HDMI TX can run at fixed clock with the video valid (vid_valid) toggling from the RX
- Video in and out use the same clock check box in the HDMI TX core Advanced Configuration table is turned on
- HDMI 2.1 TX-TX Retransmit Design with video frame buffer
- Fixed 225 MHz for RX video clock
- TX video clock running at a frequency relative to the actual pixel clock (pixel clock/pixel-in-parallel)
- Video frame buffer between RX and TX truncates or repeats the frame for the asynchronous clocking between RX and TX
Both design variants currently only support FRL mode. Intel will enable support for TMDS mode in a future release.