Questa* Intel® FPGA Edition Quick-Start: Intel® Quartus® Prime Standard Edition

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ID 703090
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition) 2. Known Differences Between the Questa* Intel® FPGA Edition and ModelSim* - Intel® FPGA Edition 3. Questa* Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Standard Edition Revision History
1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition) x
1.1. Prerequisites 1.2. Open the Example Design 1.3. Specify EDA Tool Settings 1.4. Launch Simulation 1.5. View Signal Waveforms 1.6. Add Signals to the Simulation 1.7. Rerun Simulation
1. Questa* Intel® FPGA Edition Simulation Quick-Start ( Intel® Quartus® Prime Standard Edition)
2. Known Differences Between the Questa* Intel® FPGA Edition and ModelSim* - Intel® FPGA Edition
3. Questa* Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Standard Edition Revision History

1.6. Add Signals to the Simulation

The CLOCK, WE, OFFSET, RESET_N, and RD_DATA signals automatically appear in the Wave window because the top-level design defines these I/O. In addition, you can optionally add internal signals to the simulation.
Perform the following steps to add signals to the simulation:
  1. In the Objects window, locate the UP_module, DOWN_module, PLL_module, and RAM_module modules.
  2. In the Objects window, select RAM_module to view the module's inputs and outputs.
    Figure 9. Add Signals to the Wave Window
  3. Right-click rdaddress and then click Add Wave to add the internal signals between the down-counter and dual-port RAM module.
  4. Right-click wraddress and then click Add Wave to add the internal signals between the up-counter and dual-port RAM module. Alternatively, you can drag and drop these signals from the Objects window to the Wave window.
  5. Click Simulate > Run > Continue to generate waveforms for the new signals you added.
Level Two Title