Resource Usage for the DC-DC Converter Design Example

AN 959: DC-DC Converter Design Example

Download PDF

ID 703007

Date 11/12/2021

Version current

Public

Visible to Intel only — GUID: quw1633439526457

Ixiasoft

The design can run at different clock frequencies up to 125 MHz.

Table 1. Resource Usage for DC-DC Converter Design ExampleAt different clock frequencies
Frequency (MHz)	LEs	Registers	Memory Bits	M9Ks	Embedded Multiplier 9-bit elements	Latency (FPGA clock cycles)	Latency (ns)
10	1,553	363	0	0	12	7	700
20	1,562	424	0	0	12	8	400
50	1,713	679	135	1	10	15	300
100	1,949	1115	162	1	10	24	240
125	1,762	1049	486	2	10	28	224

Table 2. Resource Usage for DC-DC Converter Design ExampleFor PI controller and PWM comparison at different clock frequencies
Frequency (MHz)	LEs	Registers	Embedded Multiplier 9-bit elements	Latency (FPGA clock cycles)	Latency (ns)
10	610	122	0	1	100
20	611	135	0	1	50
50	709	168	4	6	120
100	742	284	4	10	100
125	689	323	0	12	96