AN 959: DC-DC Converter Design Example

ID 703007
Date 11/12/2021
Public

Generating VHDL for the DC-DC Converter Design Example

The control and hardware simulator VHDL code targets the Intel MAX 10 FPGA Development Board.
  1. Start DSP Builder for Intel FPGAs.
  2. Change the directory to the matlab.
  3. Double click vvc_hwsim_adsp_vhdl.mdl to load the model.
  4. Click Simulation > Start.
    DSP Builder for Intel FPGAs generates the VHDL files in matlab\rtl.