F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

3.5.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

Refer to the instructions in Generating the Design.

Note: Running the hardware test with the design generated as-is is only possible when the F-Tile JESD204C Intel® FPGA IP is configured in duplex data path mode (i.e., with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 22.   Intel Agilex® 7 I-Series Transceiver-SoC Development Kit Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards.
Port Name Port Description Board Component Component Description
global_rst_n Global reset U3C Refer to Intel® MAX® 10 Device Data Sheet.
refclk_core Core PLL reference clock input U18 Si5391-A clock generator (OUT0)
refclk_xcvr Transceiver reference clock input U18 Si5391-A clock generator (OUT0)
mgmt_clk Control clock U19 Si5391-A clock generator (OUT6)
tx_serial_data TX serial data J7 FMC+ connector (F-Tile Bank 12C)
rx_serial_data RX serial data J7 FMC+ connector (F-Tile Bank 12C)
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