F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

3.1.9. Pattern Generator and Checker

The pattern generator and checker are useful for creating data samples and monitoring for testing purposes.
Table 12.  Supported Pattern Generator
Pattern Generator Description
PRBS pattern generator

The F-Tile JESD204C design example PRBS pattern generator supports the following degree of polynomials:

  • PRBS23: X23+X18+1
  • PRBS15: X15+X14+1
  • PRBS9: X9+X5+1
  • PRBS7: X7+X6+1
Ramp pattern generator

The ramp pattern value increments by 1 for every subsequent sample with the generator width of N, and rolls over to 0 when all bits in the sample are 1.

Enable the ramp pattern generator by writing a 1 to bit 2 of the tst_ctl register of the ED control block.

Command channel ramp pattern generator

The F-Tile JESD204C design example supports command channel ramp pattern generator per lane. The ramp pattern value increments by 1 per 6 bits of command words.

The starting seed is an increment pattern across all lanes.
Table 13.  Supported Pattern Checker
Pattern Checker Description
PRBS pattern checker

The scrambling seed in the pattern checker is self-synchronized when the F-Tile JESD204C IP achieves deskew alignment. The pattern checker requires 8 octets for the scrambling seed to self-synchonize.

Ramp pattern checker

The first valid data sample for each converter (M) is loaded as the initial value of the ramp pattern. Subsequent data samples values must increase by 1 in each clock cycle up to the maximum and then roll over to 0.

For example, when S=1, N=16 and WIDTH_MULP = 2, the data width per converter is S * WIDTH_MULP * N = 32. The maximum data sample value is 0xFFFF. The ramp pattern checker verifies that identical patterns are received across all converters.

Command channel ramp pattern checker

The F-Tile JESD204C design example supports command channel ramp pattern checker. The first command word (6 bits) received is loaded as the initial value. Subsequent command words in the same lane must increment up to 0x3F and roll over to 0x00.

The command channel ramp pattern checker checks for ramp patterns across all lanes.

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