F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

3.5. Hardware Test for System Console Control Design Example

Perform the following instructions to run the hardware test for the design example using the system console control in the Intel® Quartus® Prime software.
Note: This hardware test assumes that you configured your design in duplex mode for system console control. Make your own modifications if you're using simplex mode design.
  1. Launch the System Console tool from Intel® Quartus® Prime (Tools > System Debugging Tools > System Console).
  2. In the TCL Console command prompt, type get_service_paths master to print a list of devices connected to your JTAG chain.
  3. Open the main.tcl script located in the ed/hwtest/ directory in any text editor of your choice and locate the following line. 
    set master_index [expr {$master_list_length - 1}]
  4. Adjust the master_index offset as necessary to reflect your JTAG chain configuration such that the master_index always points to the Intel Agilex® 7 device and save the file.
    Figure 10. Example of master_index Configurations to Reflect JTAG Chain
  5. In the TCL Console command prompt, navigate to the ed/hwtest/ directory (cd../ed/hwtest/) and execute the main.tcl script (source main.tcl). Your TCL Console window should resemble the following figure.
    Figure 11. Source main.tcl
  6. Type start_basic_test at the command prompt to execute the link setup and test procedure.

    This procedure executes a set of instructions to set up sysref on TX and RX as periodic, check PRBS pattern, configure the F-Tile JESD204C IP PHY internal serial loopback mode and report link status.

    The following figure illustrates the expected result from a successful link setup and test for a variant of L=8, M=2, and F=1 with a data rate of 24.33024 Gbps.
    Figure 12. Successful Test in the System Console
    Table 21.  Procedures in the main.tcl System Console Script The table describes useful procedures in the main.tcl that may be helpful in debugging.
    Procedure Values Description
    get_service_paths {master} Reports all devices that are connected to the JTAG chain. Use this information to set the master index to point to the Intel Agilex® 7 device.
    get_master_index N/A Sets the targeted device master index. Use get_service_paths master to determine the offset of the Intel Agilex® 7 device in the JTAG chain, and edit the offset in this procedure accordingly.
    start_basic_test N/A Procedure that executes a set of instructions to set up SYSREF on TX and RX as periodic, check PRBS pattern, configure the F-Tile JESD204C IP PHY internal serial loopback mode, configure PMA and to report link status.
    reset N/A Global reset
    xcvr_lpbk {0,1}

    0: Disables internal serial loopback

    1: Enables internal serial loopback
    testmode {ramp, prbs7, prbs9, prbs15, prbs23 }

    ramp: Sets pattern generator and checker to ramp pattern

    prbs7-23: Set pattern generator and checker to the respective PRBS patterns
    sysref_type {oneshot, periodic, gperiodic } Sets the SYSREF type
    eval_test N/A

    1. Loads status.

    2. Checks lane by lane.

    3. Shows the TX and RX registers values:

    • rst_sts0:
      • Bit 0 – CORE PLL LOCKED
    • rx_status3:
      • Bit 0-15 – RX CDR LOCKED
    • rx_status4:

      • Bit 0-15 – SH LOCKED

    • rx_status5:
      • Bit 0-15 – EMB LOCKED
    • tst_err0:
      • Bit 0 – PATTERN CHECKER ERROR
      • Bit 1 – TX LINK ERROR
      • Bit 2 – RX LINK ERROR
      • Bit 3 – COMMAND PATTERN CHECKER ERROR
    read_err_status N/A Reads F-Tile JESD204C IP error status registers.
    clear_err_status N/A Clears F-Tile JESD204C IP error status registers
    read_rx_status0 N/A Reads F-Tile JESD204C IP rx_status0 register.
    read_tx_status0 N/A Reads F-Tile JESD204C IP tx_status0 register.
    read_rx_syncn_sysref_ctrl N/A Reads F-Tile JESD204C IP syncn_sysref_ctrl register.
    wait_seconds {integer} Waits for {integer} seconds.
    wait_minutes {integer} Waits for {integer} minutes.

Section Content
Board Connectivity

Level Two Title