F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 2.2.0
  • Added Aldec Riviera-PRO* simulator support:
    • Updated Hardware and Software Requirements topic.
    • Updated Directory Structure for F-Tile JESD204C Intel Agilex 7 Design Example figure.
    • Updated Directory Files table.
    • Updated Simulating the Design Example Testbench topic.
  • Updated the product family name to "Intel Agilex 7."
2023.02.10 22.3 2.0.0 Fixed the links in Table 1: Related Documents.
2022.09.27 22.3 2.0.0 Updated default device support from AGIB027R31B1E2VR0 to AGIB027R31B2E2V in Hardware and Software Requirements section.
2022.04.27 22.1 1.0.0
  • Added support for Xcelium in Hardware and Software Requirements section.
  • Removed details for Enable internal serial loopback from Parameters in the Example Design Tabtable in Design Example Parameters section.
  • Updated Directory Files table with additional information.
  • Added command for Xcelium in simulation steps in Simulating the Design Example Testbench section.
  • Updated Clock Control GUI Setting figure.
  • Updated note in Compiling and Testing the Design section.
  • Update Board Component and Component Description details in Intel Agilex I-Series Transceiver-SoC Development Kit Board Connectivity table.
2021.12.13 21.4 1.0.0
  • Added new topics:
    • Compiling and Testing the Design
    • Hardware Test for System Console Control Design Example
    • Board Connectivity
  • Updated topic title Software Requirements to Hardware and Software Requirements.
  • Updated Table: Parameters in the Example Design Tab to include the Agilex I-Series Transceiver-SoC Development Kit option under the Select board parameter.
  • Updated the list of files under the ed/rtl folder in Table: Directory Files.
  • Updated the descriptions of the following clock signals in Table: Design Example Clocks:
    • mgmt_rst_in_n
    • j204c_tx_rst_n
    • j204c_rx_rst_n
  • Updated the reset values for sysref_ctl in Table: ED Control Block Control and Status Registers.
2021.10.11 21.3 1.0.0 Initial release.
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