F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.3
IP Version 2.2.0

This user guide provides the features, usage guidelines, and detailed description about the design examples for the F-Tile JESD204C Intel® FPGA IP using Intel Agilex® 7 devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the F-Tile JESD204C Intel® FPGA IP.
Table 1.  Related Documents
Reference Description
F-Tile JESD204C Intel® FPGA IP User Guide Provides information about the F-Tile JESD204C Intel® FPGA IP.
F-Tile JESD204C Intel® FPGA IP Release Notes Lists the changes made for the F-Tile JESD204C Intel® FPGA IP in a particular release.
JESD204C Intel® FPGA IP User Guide Provides information about the F-Tile JESD204C Intel® FPGA IP.
JESD204C Intel® FPGA IP Release Notes Lists the changes made for the JESD204C Intel® FPGA IP in a particular release.
JESD204C Intel® FPGA IP Design Example User Guide Provides information about how to instantiate F-Tile JESD204C design examples using Intel Agilex® 7 F-tile devices.

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel Agilex® 7 devices.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
LEMC Local Extended Multiblock Clock
FC Frame clock rate
ADC Analog to Digital Converter
DAC Digital to Analog Converter
DSP Digital Signal Processor
TX Transmitter
RX Receiver
DLL Data link layer
CSR Control and status register
CRU Clock and Reset Unit
ISR Interrupt Service Routine
FIFO First-In-First-Out
SERDES Serializer Deserializer
ECC Error Correcting Code
FEC Forward Error Correction
SERR Single Error Detection (in ECC, correctable)
DERR Double Error Detection (in ECC, fatal)
PRBS Pseudorandom binary sequence
MAC Media Access Controller. MAC includes protocol sublayer, transport layer, and data link layer.
PHY Physical Layer. PHY typically includes the physical layer, SERDES, drivers, receivers and CDR.
PCS Physical Coding Sub-layer
PMA Physical Medium Attachment
RBD RX Buffer Delay
UI Unit Interval = duration of serial bit
RBD count RX Buffer Delay latest lane arrival
RBD offset RX Buffer Delay release opportunity
SH Sync header
TL Transport layer
EMIB Embedded Multi-die Interconnect Bridge
Table 3.  Glossary List
Term Description
Converter Device ADC or DAC converter
Logic Device FPGA or ASIC
Octet A group of 8 bits, serving as input to 64/66 encoder and output from the decoder
Nibble A set of 4 bits which is the base working unit of JESD204C specifications
Block A 66-bit symbol generated by the 64/66 encoding scheme
Link Clock

Link Clock = Lane Line Rate/66.
Frame A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal.
Frame Clock A system clock which runs at the frame's rate, that must be 1x and 2x link clock.
Samples per frame clock

Samples per clock, the total samples in frame clock for the converter device.

LEMC Internal clock used to align the boundary of the extended multiblocks between lanes and into the external references (SYSREF or Subclass 1).
Subclass 0 No support for deterministic latency. Data should be immediately released upon lane to lane deskew on receiver.
Subclass 1 Deterministic latency using SYSREF.
Multipoint Link Inter-device links with 2 or more converter devices.
64B/66B Encoding Line code that maps 64-bit data to 66 bits to form a block. The base level data structure is a block that starts with 2-bit sync header.
Table 4.  Symbols
Term Description
L Number of lanes per converter device
M Number of converters per device
F Number of octets per frame on a single lane
S Number of samples transmitted per single converter per frame cycle
N Converter resolution
N’ Total number of bits per sample in the user data format
CS Number of control bits per conversion sample
CF Number of control words per frame clock period per link
HD High Density user data format
E Number of multiblocks in an extended multiblock
Level Two Title