Technology |
- Low-cost, low-power FPGA fabric
- 1.0 V and 1.2 V core voltage options
- Available in commercial, industrial, and automotive temperature grades
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Packaging |
- Several package types and footprints:
- FineLine BGA (FBGA)
- Enhanced Thin Quad Flat Pack (EQFP)
- Ultra FineLine BGA (UBGA)
- Micro FineLine BGA (MBGA)
- Multiple device densities with pin migration capability
- RoHS6 compliance
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Core architecture |
- Logic elements (LEs)—four-input look-up table (LUT) and register
- Abundant routing/metal interconnect between all LEs
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Internal memory blocks |
- M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable
- Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM
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Embedded multiplier blocks |
- One 18 × 18 or two 9 × 9 multiplier modes, cascadable
- Complete suite of DSP IPs for algorithmic acceleration
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Clock networks |
- Global clocks that drive throughout entire device, feeding all device quadrants
- Up to 15 dedicated clock pins that can drive up to 20 global clocks
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Phase-locked loops (PLLs) |
- Up to four general purpose PLLs
- Provides robust clock management and synthesis
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General-purpose I/Os (GPIOs) |
- Multiple I/O standards support
- Programmable I/O features
- True LVDS and emulated LVDS transmitters and receivers
- On-chip termination (OCT)
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SEU mitigation |
SEU detection during configuration and operation |
Configuration |
- Active serial (AS), passive serial (PS), fast passive parallel (FPP)
- JTAG configuration scheme
- Configuration data decompression
- Remote system upgrade
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