Cyclone® 10 LP Device Overview

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ID 683879
Date 5/27/2022
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Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview x
Summary of Intel® Cyclone® 10 LP Features Intel® Cyclone® 10 LP Available Options Intel® Cyclone® 10 LP Maximum Resources Intel® Cyclone® 10 LP Package Plan Intel® Cyclone® 10 LP I/O Vertical Migration Logic Elements and Logic Array Blocks Embedded Multipliers Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O Configuration Power Management Document Revision History for Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview

Intel® Cyclone® 10 LP Package Plan

Table 3.   Package Plan for Intel® Cyclone® 10 LP Devices The GPIO counts do not include the DCLK pins. The LVDS counts include DIFFIO and DIFFCLK pairs only—LVDS I/Os with both p and n pins. Refer to the related information.
Device Package
Type

M164

164-pin MBGA

U256

256-pin UBGA

U484

484-pin UBGA

E144

144-pin EQFP

F484

484-pin FBGA

F780

780-pin FBGA

Size 8 mm × 8 mm 14 mm × 14 mm 19 mm × 19 mm 22 mm × 22 mm 23 mm × 23 mm 29 mm × 29 mm
Ball Pitch 0.5 mm 0.8 mm 0.8 mm 0.5 mm 1.0 mm 1.0 mm
I/O Type GPIO LVDS GPIO LVDS GPIO LVDS GPIO LVDS GPIO LVDS GPIO LVDS
10CL006 — — 176 65 — — 88 22 — — — —
10CL010 101 26 176 65 — — 88 22 — — — —
10CL016 87 22 162 53 340 137 78 19 340 137 — —
10CL025 — — 150 52 — — 76 18 — — — —
10CL040 — — — — 325 124 — — 325 124 — —
10CL055 — — — — 321 132 — — 321 132 — —
10CL080 — — — — 289 110 — — 289 110 423 178
10CL120 — — — — — — — — 277 103 525 230
Related Information
Level Two Title