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Summary of Intel® Cyclone® 10 LP Features
Intel® Cyclone® 10 LP Available Options
Intel® Cyclone® 10 LP Maximum Resources
Intel® Cyclone® 10 LP Package Plan
Intel® Cyclone® 10 LP I/O Vertical Migration
Logic Elements and Logic Array Blocks
Embedded Multipliers
Embedded Memory Blocks
Clocking and PLL
FPGA General Purpose I/O
Configuration
Power Management
Document Revision History for Intel® Cyclone® 10 LP Device Overview
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Clocking and PLL
Intel® Cyclone® 10 LP devices feature global clock (GCLK) networks, dedicated clock pins, and general purpose PLLs.
- Up to 20 GCLK networks that drive throughout the device
- Up to 15 dedicated clock pins
- Up to four general purpose PLLs with five outputs per PLL
The PLLs provide robust clock management and synthesis for the Intel® Cyclone® 10 LP device. You can dynamically reconfigure the PLLs in user mode to change the clock phase or frequency.