Cyclone® 10 LP Device Overview

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ID 683879
Date 5/27/2022
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Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview x
Summary of Intel® Cyclone® 10 LP Features Intel® Cyclone® 10 LP Available Options Intel® Cyclone® 10 LP Maximum Resources Intel® Cyclone® 10 LP Package Plan Intel® Cyclone® 10 LP I/O Vertical Migration Logic Elements and Logic Array Blocks Embedded Multipliers Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O Configuration Power Management Document Revision History for Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview

Embedded Multipliers

Each embedded multiplier block in Intel® Cyclone® 10 LP devices supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. You can cascade the multiplier blocks to form wider or deeper logic structures.

You can control the operation of the embedded multiplier blocks using the following options:

  • Parameterize the relevant IP cores with the Intel® Quartus® Prime parameter editor
  • Infer the multipliers directly with VHDL or Verilog HDL

Intel and partners offer popular DSP IPs for Intel® Cyclone® 10 LP devices, including:

  • Finite impulse response (FIR)
  • Fast Fourier transform (FFT)
  • Numerically controlled oscillator (NCO) functions

For a streamlined DSP design flow, the DSP Builder tool integrates the Intel® Quartus® Prime software with MathWorks Simulink and MATLAB design environments.

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