F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023
Public

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3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface

Table 51.  Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per InterfaceRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
FEC Enabled Split Interface Enabled29 Number of Avalon® interfaces Additional Address Bits for Decoding (K d )
0 0 1 K d =Ceiling(log2(N))
0 1 N K d =0
1 X 1 K d =0
29 Split Interface for datapath Memory mapped Avalon interface only supported for PMA Direct mode.