F-tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. F-tile Overview 2. F-tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP 6. F-tile PMA/FEC Direct PHY Design Implementation 7. Supported Tools 8. Debugging F-Tile Transceiver Links 9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2. F-tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Intel® Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA and USB mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA and USB Protocol Modes for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT Core PLL Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier 3.14.1.3. TX Equalizer Settings 3.14.1.4. TX Error Injection 3.14.1.5. RX Reconvergence 3.14.1.6. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready
4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready x
4.5.1. Example of Reference Clock Availability at Device Programming 4.5.2. Example Flow to Indicate All System PLL Reference Clocks are Ready
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP x
5.1. IP Parameters 5.2. IP Port List 5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP 5.4. Examples of Register Access Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
5.4. Examples of Register Access Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP x
5.4.1. FGT PMA Registers Access Example 5.4.2. FHT PMA Registers Access Example 5.4.3. 400G MAC/PCS Interface Registers Access Example 5.4.4. 400G FEC/PMA Interface Registers Access Example 5.4.5. 200G MAC/PCS Interface Registers Access Example 5.4.6. 200G FEC/PMA Interface Registers Access Example
6. F-tile PMA/FEC Direct PHY Design Implementation x
6.1. Implementing the F-tile PMA/FEC Direct PHY Design 6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 6.5. Enabling Custom Cadence Generation Ports and Logic 6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP 6.7. Simulating the F-Tile PMA/FEC Direct PHY Design 6.8. F-tile Interface Planning
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
6.2.1. Setting General and Common Datapath Options 6.2.2. Setting TX Datapath Options 6.2.3. Setting RX Datapath Options
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
6.7.1. PAM4 Encoding Schemes in Simulation
6.8. F-tile Interface Planning x
6.8.1. F-tile Interface Planner Usage Example
7. Supported Tools x
7.1. F-Tile Channel Placement Tool 7.2. F-Tile PMA and FEC Direct Port Mapping Calculator 7.3. F-Tile Clocking and Datapath Tool 7.4. F-Tile TX Equalizer Tool
8. Debugging F-Tile Transceiver Links x
8.1. F-Tile Transceiver Toolkit GUI 8.2. F-Tile Transceiver Debugging Flow Walkthrough 8.3. Transceiver Toolkit Parameter Settings 8.4. Troubleshooting Common Errors 8.5. Transceiver Toolkit Scripts
8.1. F-Tile Transceiver Toolkit GUI x
8.1.1. Collection View
8.2. F-Tile Transceiver Debugging Flow Walkthrough x
8.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 8.2.2. Programming the Design into an Intel FPGA 8.2.3. Loading the Design to the Transceiver Toolkit 8.2.4. Creating Transceiver Links 8.2.5. Running BER Tests 8.2.6. Running Eye Viewer Tests 8.2.7. Running Link Optimization Tests
8.5. Transceiver Toolkit Scripts x
8.5.1. Supported Transceiver Toolkit Scripts 8.5.2. Modifying the Scripts 8.5.3. Script Execution 8.5.4. Example of the Results in Tcl Console
1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide

4.1. IP Parameters

Table 89.   F-Tile Reference and System PLL Clocks Intel® FPGA IP Parameters
Parameter Values Description
System PLL #0
Mode of system PLL 0, 1, 2 Selects the mode of system PLL #0.
  • Disabled— system PLL not used. You must enable at least one system PLL.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq>—presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq>— presets for PCIe use cases. output_freq is the system PLL output frequency.
  • User configuration—manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in non PCIe use cases when other Ethernet presets do not meet requirement.
  • User PCIe-based configuration— manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in PCIe use cases when PCIe presets do not meet requirement.
The frequency number in the preset’s label are abbreviated; they are not full precise frequency. Refer to the table below for full frequency. The default value is ETHERNET_FREQ_805_156.
User configuration
User PCIe-based configuration
ETHERNET_FREQ_805_156
ETHERNET_FREQ_805_312
ETHERNET_FREQ_805_322 41.
ETHERNET_FREQ_830_156
ETHERNET_FREQ_830_312
PCIE_FREQ_1000
PCIE_FREQ_500
PCIE_FREQ_550
PCIE_FREQ_600
PCIE_FREQ_650
PCIE_FREQ_700
PCIE_FREQ_750
PCIE_FREQ_800
PCIE_FREQ_850
PCIE_FREQ_900
PCIE_FREQ_950
Reference clock source Reference clock #0 Selects the logical reference clock source for system PLL #0. The reference clock source can be shared with FGT PMA and other system PLLs. The default value is Reference clock #0.
Reference clock #1
Reference clock #2
Reference clock #3
Reference clock #4
Reference clock #5
Reference clock #6
Reference clock #7
Reference clock #8
Reference clock #9
Output frequency 31.25 to 1000 MHz Specifies the output frequency of the system PLL #0 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, specify the exact frequency with decimal points. The default value is 805.6640625.
Refclk is available at device configuration On/Off

Indicates whether the reference clock that drives the system PLL is running and stable at device programming time.

When On, you must provide a stable reference clock at device programming time, otherwise system PLL can lock to board noise and have unstable performance.

When Off, the reference clock can take additional time to be available or stable after device programming time. The system PLL does not lock until the Global Avalon® memory-mapped interface write operation indicates that all reference clocks are ready.

The default value is On.
Note: Refer to Guidelines to Indicate all System PLL Reference Clocks are Ready for more details.
System PLL #1
Mode of system PLL 0, 1, 2 Selects the mode of system PLL #1.
  • Disabled— system PLL not used. You must enable at least one system PLL.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq>—presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq>— presets for PCIe use cases. output_freq is the system PLL output frequency.
  • User configuration—manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in non PCIe use cases when other Ethernet presets do not meet requirement.
The default value is Disabled.
User configuration
User PCIE-based configuration
ETHERNET_FREQ_805_156
ETHERNET_FREQ_805_312
ETHERNET_FREQ_805_322 41.
ETHERNET_FREQ_830_156
ETHERNET_FREQ_830_312
ETHERNET_FREQ_830_312
PCIE_FREQ_1000
PCIE_FREQ_500
PCIE_FREQ_550
PCIE_FREQ_600
PCIE_FREQ_650
PCIE_FREQ_700
PCIE_FREQ_750
PCIE_FREQ_800
PCIE_FREQ_850
PCIE_FREQ_900
PCIE_FREQ_950
Reference clock source Reference clock #0 Selects the logical reference clock source for system PLL #1. The reference clock source can be shared with FGT PMA and other system PLLs.
Reference clock #1
Reference clock #2
Reference clock #3
Reference clock #4
Reference clock #5
Reference clock #6
Reference clock #7
Reference clock #8
Reference clock #9
Output frequency 31.25 to 1000 MHz Specifies the output frequency of the system PLL #1 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points.
Refclk is available at device configuration On/Off

Indicates whether the reference clock that drives the system PLL is running and stable at device programming time.

When On, you must provide a stable reference clock at device programming time, otherwise system PLL can lock to board noise and have unstable performance.

When Off, the reference clock can take additional time to be available or stable after device programming time. The system PLL does not lock until the Global Avalon® memory-mapped interface write operation indicates that all reference clocks are ready.

The default value is On.
Note: Refer to Guidelines to Indicate all System PLL Reference Clocks are Ready for more details.
System PLL #2
Mode of system PLL 0, 1, 2 Selects the mode of system PLL #2.
  • Disabled— system PLL not used.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq>—presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq>— presets for PCIe use cases. output_freq is the system PLL output frequency.
  • User configuration—manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in non PCIe use cases when other Ethernet presets do not meet requirement.
  • User PCIe-based configuration— manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in PCIe use cases when PCIe presets do not meet requirement.
The frequency number in the Preset’s label are abbreviated, they are not full precise frequency.
User configuration
User PCIE-based configuration
ETHERNET_FREQ_805_156
ETHERNET_FREQ_805_312
ETHERNET_FREQ_805_322 41.
ETHERNET_FREQ_830_156
ETHERNET_FREQ_830_312
ETHERNET_FREQ_830_312
PCIE_FREQ_1000
PCIE_FREQ_500
PCIE_FREQ_550
PCIE_FREQ_600
PCIE_FREQ_650
PCIE_FREQ_700
PCIE_FREQ_750
PCIE_FREQ_800
PCIE_FREQ_850
PCIE_FREQ_900
PCIE_FREQ_950
Reference clock source Reference clock #0 Selects the logical reference clock source for system PLL #2. The reference clock source can be shared with FGT PMA and other system PLLs.
Reference clock #1
Reference clock #2
Reference clock #3
Reference clock #4
Reference clock #5
Reference clock #6
Reference clock #7
Reference clock #8
Reference clock #9
Output Frequency 31.25 to 1000 MHz Specifies the output frequency of the system PLL #2 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points.
Refclk is available at device configuration On/Off

Indicates whether the reference clock that drives the system PLL is running and stable at device programming time.

When On, you must provide a stable reference clock at device programming time, otherwise system PLL can lock to board noise and have unstable performance.

When Off, the reference clock can take additional time to be available or stable after device programming time. The system PLL does not lock until the Global Avalon® memory-mapped interface write operation indicates that all reference clocks are ready.

The default value is On.
Note: Refer to Guidelines to Indicate all System PLL Reference Clocks are Ready for more details.
FHT Common PLL
Controller source Auto, CommonPLL A, CommonPLL B

If both common PLLs are enabled, this selection specifies the common PLL that drives the FHT microcontroller. The reference clock that drives this common PLL must be present and stable throughout F-tile operation.

FHT Common PLL A
Enable FHT Common PLL A On/Off Enable/Disable FHT common PLL A. When enabled, must provide FHT reference clock source and frequency. The default value is Off.
FHT reference clock source FHT reference clock #0 Specifies the logical reference clock source for FHT common PLL A. The default value is FHT reference clock #0.
FHT reference clock #1
FHT Common PLL B
Enable FHT Common PLL B On/Off When enabled, must provide FHT reference clock source and frequency. The default value is Off.
FHT reference clock source FHT reference clock #0 Specifies the logical reference clock source for FHT common PLL B. The default value is FHT Reference clock #0.
FHT reference clock #1
Reference clock(s)
FGT/System PLL
Enable reference clock #0 for FGT PMA On/Off Enables logical reference clock #0 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #0 25 to 380 MHz Specifies the reference clock #0 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #0 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is 156.25 MHz.
Enable Reference clock #1 for FGT PMA On/Off Enables logical reference clock #1 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #1 25 to 380 MHz Specifies the reference clock #1 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA
When reference clock #1 is shared between FGT PMA and system PLL, reference clock frequency changes to drop-down of calculated legal frequencies and user must select one from drop-down. The default value is Disabled.
Enable Reference clock #2 for FGT PMA On/Off Enable logical reference clock #2 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #2 25 to 380 MHz Specifies the reference clock #2 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA
When reference clock #2 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #3 for FGT PMA On/Off Enable logical reference clock #3 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #3 25 to 380 MHz Specifies the reference clock #3 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA
When reference clock #3 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #4 for FGT PMA On/Off Enable logical reference clock #4 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #4 25 to 380 MHz Specifies the reference clock #4 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #4 is shared between FGT PMA and system PLL, , the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #5 for FGT PMA On/Off Enable logical reference clock #5 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #5 25 to 380 MHz Specifies the reference clock #5 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #5 is shared between FGT PMA and system PLL, , the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #6 for FGT PMA On/Off Enable logical reference clock #6 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #6 25 to 380 MHz Specifies the reference clock #6 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #6 is shared between FGT PMA and system PLL, , the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #7 for FGT PMA On/Off Enable logical reference clock #7 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #7 25 to 380 MHz Specifies the reference clock #7 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #7 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #8 for FGT PMA On/Off Enable logical reference clock #8 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #8 25 to 380 MHz Specifies the reference clock #8 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #8 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. . The default value is Disabled.
Enable Reference clock #9 for FGT PMA On/Off Enable logical reference clock #9 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #9 25 to 380 MHz Specifies the reference clock #9 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #9 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. . The default value is Disabled.
FGT CDR Clock-out(s)
Enable FGT CDR Output #0 On/Off Enables logical FGT CDR clock output #0. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off.
Enable FGT CDR Output #1 On/Off Enables logical FGT CDR clock output #1. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off.
FHT Reference clock(s)
FHT Reference clock frequency #0 100 to 200 MHz Specifies the FHT reference clock #0 frequency in MHz.
FHT Reference clock frequency #1 100 to 200 MHz Specifies the FHT reference clock #1 frequency in MHz.
41 This mode is not currently supported
Level Two Title