F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023
Public

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4.5.2. Example Flow to Indicate All System PLL Reference Clocks are Ready

You need to have the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP instantiated in your design. Please refer to Implementing the F-Tile Global Avalon® memory-mapped interface Intel FPGA IP for more details.

Here are the steps to indicate all System PLL reference clocks are ready:
  1. Wait until all the system PLL's reference clocks are available and stable.
  2. Write register 0xffff8 with value 0x90000000 using the Global Avalon® memory-mapped interface to indicate that all the system PLL's reference clocks are ready.
  3. Read register 0xffff4 using the Global Avalon® memory-mapped interface to confirm that the previous write operation has been correctly received and responded by the system PLL.
    • If the read value is 0x80000000 or 0xa0000000, all enabled system PLLs are locked.
    • If the read value is 0x90000000, the reference clock frequency is not accurate.
    • If the read value is 0xb0000000, no system PLL has the Refclk is available at device configuration parameter set to Off and write operation in step 2 is invalid.