F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 4/03/2023
Public

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4.5.1. Example of Reference Clock Availability at Device Programming

All enabled system PLLs need to have the Refclk is available at device configuration parameter set to the same value. Only the following two situations are supported.
  • All enabled system PLLs have Refclk is available at device configuration parameter set to On.
  • Or all enabled system PLLs have Refclk is available at device configuration parameter set to Off.
The following examples demonstrate the reference clock behavior during device programming.
In the following example:
Table 93.  Example 1 of System PLL and Reference Clock Availability
System PLL #N Mode of System PLL Refclk is available at device configuration
0 Disabled N/A
1 User Configuration On
2 PCIE_FREQ_100 On
  • System PLL #0 is not used.
  • System PLL #1 locks automatically at device programming without the Global Avalon® memory-mapped interface write operations.
  • System PLL #2 locks automatically at device programming without the Global Avalon® memory-mapped interface write operations.
In the following example:
Table 94.  Example 2 of System PLL and Reference Clock Availability
System PLL #N Mode of System PLL Refclk is available at device configuration
0 PCIE_FREQ_1000 Off
1 ETHERNET_FREQ_805_156 Off
2 User PCIE-based Configuration Off
  • System PLL #0 does not lock without the Global Avalon® memory-mapped interface write operations.
  • System PLL #1 does not lock without the Global Avalon® memory-mapped interface write operations.
  • System PLL #2 does not lock without the Global Avalon® memory-mapped interface write operations.
  • Device programming takes longer and all channels on this F-tile stay reset until the Global Avalon® memory-mapped interface write operations are completed.