Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

Download PDF
ID 683870
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Intel FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
1. Intel FPGA Simulation Basics x
1.1. Intel FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Types 1.5. Supported Hardware Description Languages 1.6. Supported Simulators 1.7. Post-Fit Simulation Support by Intel FPGA Family 1.8. Intel FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Intel® Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. Intel FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Intel® Quartus® Prime Simulation Library x
1.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. QuestaSim* Simulation Setup Script Example 2.4. Sourcing QuestaSim* Simulator Setup Scripts 2.5. Unsupported Features 2.6. QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. Intel FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

3.3. VCS Simulation Setup Script Example

The Intel® Quartus® Prime software can generate a simulation setup script for IP cores in your design. The scripts contain shell commands that compile the required simulation models in the correct order, elaborate the top-level design, and run the simulation for 100 time units by default. You can run these scripts from a Linux command shell.

The scripts for VCS and VCS MX are vcs_setup.sh (for Verilog HDL or SystemVerilog) and vcsmx_setup.sh (combined Verilog HDL and SystemVerilog with VHDL). Read the generated .sh script to see the variables that are available for override when sourcing the script or redefining directly if you edit the script. To set up the simulation for a design, use the command-line to pass variable values to the shell script.

Using Command-line to Pass Simulation Variables

sh vcsmx_setup.sh\
USER_DEFINED_ELAB_OPTIONS=+rad\
USER_DEFINED_SIM_OPTIONS=+vcs+lic+wait

Example Top-Level Simulation Shell Script for VCS-MX

# Run generated script to compile libraries and IP simulation files
# Skip elaboration and simulation of the IP variation
sh ./ip_top_sim/synopsys/vcsmx/vcsmx_setup.sh SKIP_ELAB=1 SKIP_SIM=1 QSYS_SIMDIR="./ip_top_sim"
#Compile top-level testbench that instantiates IP
vlogan -sverilog ./top_testbench.sv
#Elaborate and simulate the top-level design 
vcs –lca –t ps <elaboration control options> top_testbench
simv <simulation control options>

Example Top-Level Simulation Shell Script for VCS

# Run script to compile libraries and IP simulation files
sh ./ip_top_sim/synopsys/vcs/vcs_setup.sh TOP_LEVEL_NAME=”top_testbench”\
# Pass VCS elaboration options to compile files and elaborate top-level
 passed to the script as the TOP_LEVEL_NAME
USER_DEFINED_ELAB_OPTIONS="top_testbench.sv"\
# Pass in simulation options and run the simulation for specified amount of time.
USER_DEFINED_SIM_OPTIONS=”<simulation control options>
Level Two Title