Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 12/04/2023
Public

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Document Table of Contents

2.2.3. Generating Signal Activity Data for Power Analysis

To generate and use simulation signal activity data for power analysis:

  1. To run full compilation on your design, click Processing > Start Compilation.
  2. To specify settings for simulation output, click Assignments > Settings > EDA Tool Settings > Simulation. Select your simulator in Tool name and the Format for output netlist and Output directory.
    Figure 7. EDA Tool Settings for Simulation


  3. Turn on Map illegal HDL characters. This setting directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL, and results in more accurate data for power analysis.
  4. Click the Power Analyzer Settings page.
  5. Under Input file, turn on Use input files to initialize toggle rates and static probabilities during power analysis.
    Figure 8. Specifying Power Analysis Input Files
  6. To specify a .vcd for power analysis, click Add and specify the File name, Entity, and Simulation period for the .vcd, and click OK.
  7. To enable glitch filtering during power analysis with the .vcd you generate, turn on Perform glitch filtering on VCD files.
  8. To run the power analysis, click Start on the Power Analysis step in the Compilation Dashboard. View the toggle rates in the power analysis results.