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Answers to Top FAQs
1. Intel FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
1.1. Intel FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Types
1.5. Supported Hardware Description Languages
1.6. Supported Simulators
1.7. Post-Fit Simulation Support by Intel FPGA Family
1.8. Intel FPGA Simulation Basics Revision History
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2.2.3. Generating Signal Activity Data for Power Analysis
To generate and use simulation signal activity data for power analysis:
- To run full compilation on your design, click Processing > Start Compilation.
- To specify settings for simulation output, click Assignments > Settings > EDA Tool Settings > Simulation. Select your simulator in Tool name and the Format for output netlist and Output directory.
Figure 7. EDA Tool Settings for Simulation
- Turn on Map illegal HDL characters. This setting directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL, and results in more accurate data for power analysis.
- Click the Power Analyzer Settings page.
- Under Input file, turn on Use input files to initialize toggle rates and static probabilities during power analysis.
Figure 8. Specifying Power Analysis Input Files
- To specify a .vcd for power analysis, click Add and specify the File name, Entity, and Simulation period for the .vcd, and click OK.
- To enable glitch filtering during power analysis with the .vcd you generate, turn on Perform glitch filtering on VCD files.
- To run the power analysis, click Start on the Power Analysis step in the Compilation Dashboard. View the toggle rates in the power analysis results.