Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Intel FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
1. Intel FPGA Simulation Basics x
1.1. Intel FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Types 1.5. Supported Hardware Description Languages 1.6. Supported Simulators 1.7. Post-Fit Simulation Support by Intel FPGA Family 1.8. Intel FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Intel® Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. Intel FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Intel® Quartus® Prime Simulation Library x
1.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. QuestaSim* Simulation Setup Script Example 2.4. Sourcing QuestaSim* Simulator Setup Scripts 2.5. Unsupported Features 2.6. QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. Intel FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

1.3.6. Intel FPGA Simulation Generic Workflow

The following describes the high level workflow for simulation of any Intel® Quartus® Prime design using any supported simulator:

Figure 6. Generic Intel FPGA Simulation Workflow


  1. Identify all of the HDL simulation files, including design files, simulation library files, and HDL testbench files.
  2. Identify the top-level test bench module for simulation.
  3. For each HDL simulation file, determine the logical library for compilation, and any compilation options for compiling the file.1
  4. Determine any simulator-specific elaboration options required for elaborating the top- level testbench module, as Understanding Elaboration describes.
  5. Use the information gathered in previous steps to assemble a simulation script to compile, elaborate, and simulate the design. This script must include commands to perform the following:
    • Compile the simulation files into libraries, as Compiling Files into Library Directories describes.
    • Elaborate the Top-Level testbench, as Understanding Elaboration describes.
    • Run the executable simulation model to simulate the testbench and the design, using the appropriate commands for your simulator to configure and run simulation.

The Intel® Quartus® Prime software can generate simulator-specific simulation scripts to automate some of the simulation processing in your preferred simulation environment.

The Intel® Quartus® Prime software can generate a simulator specific simulation script for an IP core, or a Platform Designer system, for use in RTL simulation. The script includes commands to compile all the IP RTL files, as well as an elaboration command with any simulator specific options.

The Intel® Quartus® Prime software can generate a simulation library compilation script for a given simulator, device family, and language. This script includes commands to compile the simulation library files for the specified simulator, device family, and language. You can use this script for RTL simulation and gate-level simulation.

1 In general, you can compile most HDL simulation files into the default work library.
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