Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Intel FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
1. Intel FPGA Simulation Basics x
1.1. Intel FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Types 1.5. Supported Hardware Description Languages 1.6. Supported Simulators 1.7. Post-Fit Simulation Support by Intel FPGA Family 1.8. Intel FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Intel® Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. Intel FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Intel® Quartus® Prime Simulation Library x
1.3.3.1. The Intel® Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. QuestaSim* Simulation Setup Script Example 2.4. Sourcing QuestaSim* Simulator Setup Scripts 2.5. Unsupported Features 2.6. QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. Intel FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

1.8. Intel FPGA Simulation Basics Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.12.07 23.4
  • Added new Post-Fit Simulation by Intel FPGA Family topic.
  • Updated simulator versions supported in Supported Simulators topic.
2023.10.02 23.3
  • Replaced all content in chapter with newly developed content more suitable for basic understanding of FPGA design simulation.
  • Updated chapter to reflect end of support for ModelSim and relocation of Questa* Intel® FPGA Edition information to new Questa* Intel® FPGA Edition Simulation User Guide.
2022.12.21 22.4
  • Updated simulator versions supported in Simulator Support topic.
  • Added note about longer compilation times to Compiling Simulation Module Libraries topic.
2022.04.13 22.1
  • Updated simulator versions supported in Simulator Support topic.
  • Revised name of Questa* Intel® FPGA Edition and QuestaSim for latest guidelines throughout.
  • Updated default output directory name to questa in Using the EDA Netlist Writer topic.
2021.10.05 21.3
  • Revised Generating IP Simulation Files steps to include generation of all IP in the design at once.
2021.10.04 21.3
  • Changed chapter title to FPGA Simulation Basics from Simulating Intel FPGA Designs.
  • Added support for Questa* Intel® FPGA Edition simulator throughout.
  • Removed support for ModelSim - Intel FPGA Edition simulator throughout.
  • Updated simulator versions supported in Simulator Support topic.
  • Added precompiled libraries footnote to Supported Hardware Description Languages and Compiling Simulation Model Libraries topics.
  • Revised Running a Simulation (Custom Flow) topic to add missing EDA Netlist Writer step and related links.
  • Replaced "Mentor Graphics" with "Siemens EDA" to reflect current company name.
  • Updated Supported Hardware Description Languages for note on schematic conversion.
  • Revised Scripting IP Simulation to correct typo in step 1.
  • Added links to Incorporating Simulator Setup Scripts from the Generated Template topic.
2021.06.21 21.2
  • Added note about X propagation limit of the Intel® Quartus® Prime-provided clock divider simulation model to the Compiling Simulation Model Libraries topic.
2021.03.29 21.1
  • Revised Generating IP Simulation Files topic for new simulation file output options.
  • Updated supported simulator versions and removed support for Cadence Incisive Enterprise* in Simulator Support topic.
2020.10.10 20.1 Renamed --rename to --module_name in The EDA Netlist Writer and Gate-level Netlists
Level Two Title