OPAE Intel FPGA Linux Device Driver Architecture Guide

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ID 683857
Date 10/02/2017
Public
Document Table of Contents
Document Table of Contents x
1. OPAE Intel® FPGA Linux Device Driver Architecture
1. OPAE Intel® FPGA Linux Device Driver Architecture x
1.1. Hardware Architecture 1.2. sysfs Files 1.3. Revision History
1.1. Hardware Architecture x
1.1.1. FPGA Management Engine (FME) 1.1.2. Port 1.1.3. Accelerator Function (AF) Unit 1.1.4. Partial Reconfiguration 1.1.5. FPGA Virtualization 1.1.6. Driver Organization 1.1.7. Application FPGA Device Enumeration 1.1.8. PCIe Driver Enumeration 1.1.9. FME Platform Device Initialization 1.1.10. Port Platform Device Initialization 1.1.11. FME IOCTLs 1.1.12. Port IOCTLs
1.1.6. Driver Organization x
1.1.6.1. PCIe Module Device Driver 1.1.6.2. PCIe Module Device Driver Functions 1.1.6.3. FME Platform Module Device Driver 1.1.6.4. FME Platform Module Device Driver Functions 1.1.6.5. Port Platform Module Device Driver 1.1.6.6. Port Platform Module Device Driver Functions
1.1.8. PCIe Driver Enumeration x
1.1.8.1. Enumeration Data Structures 1.1.8.2. Enumeration Flow
1.1.9. FME Platform Device Initialization x
1.1.9.1. FME Platform Device Data Structures 1.1.9.2. FME Platform Device Initialization Flow
1.1.10. Port Platform Device Initialization x
1.1.10.1. Port Platform Device Data Structures 1.1.10.2. Port Platform Device Initialization Flow
1.2. sysfs Files x
1.2.1. FME Header sysfs files 1.2.2. FME Thermal Management sysfs files 1.2.3. FME Power Management sysfs files 1.2.4. FME Global Error sysfs files 1.2.5. FME Partial Reconfiguration sysfs files 1.2.6. FME Global Performance sysfs files 1.2.7. Port Header sysfs files 1.2.8. Port AFU Header sysfs files 1.2.9. Port Error sysfs files
1. OPAE Intel® FPGA Linux Device Driver Architecture

1.1. Hardware Architecture

From the OS’s point of view, the FPGA hardware appears as a regular PCIe device. The FPGA device memory is organized using a predefined data structure (Device Feature List). Features supported by the FPGA device are exposed through these data structures, as illustrated below in the following figure:
Figure 1. FPGA PCIe Device
The driver supports PCIe SR-IOV to create Virtual Functions (VFs) which can be used to assign individual accelerators to virtual machines.
Figure 2. Virtualized FPGA PCIe Device
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