Visible to Intel only — GUID: tpz1503675453644
Ixiasoft
1.1.1. FPGA Management Engine (FME)
1.1.2. Port
1.1.3. Accelerator Function (AF) Unit
1.1.4. Partial Reconfiguration
1.1.5. FPGA Virtualization
1.1.6. Driver Organization
1.1.7. Application FPGA Device Enumeration
1.1.8. PCIe Driver Enumeration
1.1.9. FME Platform Device Initialization
1.1.10. Port Platform Device Initialization
1.1.11. FME IOCTLs
1.1.12. Port IOCTLs
1.2.1. FME Header sysfs files
1.2.2. FME Thermal Management sysfs files
1.2.3. FME Power Management sysfs files
1.2.4. FME Global Error sysfs files
1.2.5. FME Partial Reconfiguration sysfs files
1.2.6. FME Global Performance sysfs files
1.2.7. Port Header sysfs files
1.2.8. Port AFU Header sysfs files
1.2.9. Port Error sysfs files
Visible to Intel only — GUID: tpz1503675453644
Ixiasoft
1.1.9.1. FME Platform Device Data Structures
struct feature_ops {
int (*init)(struct platform_device *pdev, struct feature *feature);
int (*uinit)(struct platform_device *pdev, struct feature *feature);
long (*ioctl)(struct platform_device *pdev, struct feature *feature,
unsigned int cmd, unsigned long arg);
int (*test)(struct platform_device *pdev, struct feature *feature);
};
struct feature {
const char *name;
int resource_index;
void __iomem *ioaddr;
struct feature_ops *ops;
};
struct feature_platform_data {
struct list_head node;
struct mutex lock;
unsigned long dev_status;
struct cdev cdev;
struct platform_device *dev;
unsigned int disable_count;
void *private;
int num;
int (*config_port)(struct platform_device *, u32, bool);
struct platform_device *(*fpga_for_each_port)(struct platform_device *,
void *, int (*match)(struct platform_device *, void *)); struct feature features[0];
};
struct perf_object {
int id;
const struct attribute_group **attr_groups;
struct device *fme_dev;
struct list_head node;
struct list_head children;
struct kobject kobj;
};
struct fpga_fme {
u8 port_id;
u64 pr_err;
struct device *dev_err;
struct perf_object *perf_dev;
struct feature_platform_data *pdata;
};