OPAE Intel FPGA Linux Device Driver Architecture Guide

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ID 683857
Date 10/02/2017
Public
Document Table of Contents
Document Table of Contents x
1. OPAE Intel® FPGA Linux Device Driver Architecture
1. OPAE Intel® FPGA Linux Device Driver Architecture x
1.1. Hardware Architecture 1.2. sysfs Files 1.3. Revision History
1.1. Hardware Architecture x
1.1.1. FPGA Management Engine (FME) 1.1.2. Port 1.1.3. Accelerator Function (AF) Unit 1.1.4. Partial Reconfiguration 1.1.5. FPGA Virtualization 1.1.6. Driver Organization 1.1.7. Application FPGA Device Enumeration 1.1.8. PCIe Driver Enumeration 1.1.9. FME Platform Device Initialization 1.1.10. Port Platform Device Initialization 1.1.11. FME IOCTLs 1.1.12. Port IOCTLs
1.1.6. Driver Organization x
1.1.6.1. PCIe Module Device Driver 1.1.6.2. PCIe Module Device Driver Functions 1.1.6.3. FME Platform Module Device Driver 1.1.6.4. FME Platform Module Device Driver Functions 1.1.6.5. Port Platform Module Device Driver 1.1.6.6. Port Platform Module Device Driver Functions
1.1.8. PCIe Driver Enumeration x
1.1.8.1. Enumeration Data Structures 1.1.8.2. Enumeration Flow
1.1.9. FME Platform Device Initialization x
1.1.9.1. FME Platform Device Data Structures 1.1.9.2. FME Platform Device Initialization Flow
1.1.10. Port Platform Device Initialization x
1.1.10.1. Port Platform Device Data Structures 1.1.10.2. Port Platform Device Initialization Flow
1.2. sysfs Files x
1.2.1. FME Header sysfs files 1.2.2. FME Thermal Management sysfs files 1.2.3. FME Power Management sysfs files 1.2.4. FME Global Error sysfs files 1.2.5. FME Partial Reconfiguration sysfs files 1.2.6. FME Global Performance sysfs files 1.2.7. Port Header sysfs files 1.2.8. Port AFU Header sysfs files 1.2.9. Port Error sysfs files
1. OPAE Intel® FPGA Linux Device Driver Architecture

1.1.8.2. Enumeration Flow

  • ccidrv_init()
    • Initialize fpga_ids using idr_init().
    • Initialize fpga_chrdevs[i].devt using alloc_chrdev_region().
    • Initialize fpga_class using class_create().
    • pci_register_driver(&cci_pci_driver);
  • cci_pci_probe()
    • Enable the PCI device, request access to its regions, set PCI master mode, configure DMA.
  • cci_pci_create_feature_devs() build_info_alloc_and_init()
    • Allocate a struct build_feature_devs_info, initialize it.
    • .parent_dev is set to a parent sysfs directory (intel-fpga-dev.id) that contains the FME and Port sysfs directories.
  • parse_feature_list()
    • Walk the BAR0 Device Feature List to discover the FME, the Port, and their private features.
  • parse_feature() parse_feature_afus() parse_feature_fme()
    • When an FME is encountered:
      • build_info_create_dev()
        • Allocate a platform device for the FME, storing in build_feature_devs_info.feature_dev.
        • feature_dev.id is initialized to the result of idr_alloc(fpga_ids[FME_ID],
        • feature_dev.parent is set to build_feature_devs_info.parent_dev.
        • Allocate an array of struct resource in feature_dev.resource.
      • Allocate a struct feature_platform_data, initialize it, and store a pointer in feature_dev.dev.platform_data
        • create_feature_instance() build_info_add_sub_feature()
        • Initialize feature_dev.resource[FME_FEATURE_ID_HEADER].
        • feature_platform_data_add()
        • Initialize feature_platform_data.features[FME_FEATURE_ID_HEADER], everything but .fops.
  • parse_feature() parse_feature_afus() parse_feature_port()
    • When a Port is encountered:
      • build_info_create_dev()
        • Allocate a platform device for the Port, storing in build_feature_devs_info.feature_dev.
        • feature_dev.id is initialized to the result of idr_alloc(fpga_ids[PORT_ID],
        • feature_dev.parent is set to build_feature_devs_info.parent_dev.
        • Allocate an array of struct resource in feature_dev.resource.
        • Allocate a struct feature_platform_data, initialize it, and store a pointer in feature_dev.dev.platform_data
      • build_info_commit_dev()
        • Add the struct feature_platform_data.node for the Port to the list of Ports in struct cci_drvdata.port_dev_list
      • create_feature_instance() build_info_add_sub_feature()
        • Initialize feature_dev.resource[PORT_FEATURE_ID_HEADER].
      • feature_platform_data_add()
        • Initialize feature_platform_data.features[PORT_FEATURE_ID_HEADER], everything but .fops.
  • parse_feature() parse_feature_afus() parse_feature_port_uafu()
    • – When an AFU is encountered:
      • create_feature_instance() build_info_add_sub_feature()
        • Initialize feature_dev.resource[PORT_FEATURE_ID_UAFU].
      • feature_platform_data_add()
        • Initialize feature_platform_data.features[PORT_FEATURE_ID_UAFU], everything but .fops.
  • parse_feature() parse_feature_private() parse_feature_fme_private()
    • When an FME private feature is encountered:
      • create_feature_instance() build_info_add_sub_feature()
        • Initialize feature_dev.resource[id].
      • feature_platform_data_add()
        • Initialize feature_platform_data.features[id], everything but .fops.
  • parse_feature() parse_feature_private() parse_feature_port_private()
  • When a Port private feature is encountered: * create_feature_instance() build_info_add_sub_feature() * Initialize feature_dev.resource[id]. * feature_platform_data_add() * Initialize feature_platform_data.features[id], everything but .fops.
  • parse_ports_from_fme()
    • If the driver is loaded on the Physical Function (PF), then:
      • Run the parse_feature_list() flow on each port described in the FME header.
      • Use the BAR mentioned in each Port entry in the header.
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