OPAE Intel FPGA Linux Device Driver Architecture Guide

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ID 683857
Date 10/02/2017
Public
Document Table of Contents
Document Table of Contents x
1. OPAE Intel® FPGA Linux Device Driver Architecture
1. OPAE Intel® FPGA Linux Device Driver Architecture x
1.1. Hardware Architecture 1.2. sysfs Files 1.3. Revision History
1.1. Hardware Architecture x
1.1.1. FPGA Management Engine (FME) 1.1.2. Port 1.1.3. Accelerator Function (AF) Unit 1.1.4. Partial Reconfiguration 1.1.5. FPGA Virtualization 1.1.6. Driver Organization 1.1.7. Application FPGA Device Enumeration 1.1.8. PCIe Driver Enumeration 1.1.9. FME Platform Device Initialization 1.1.10. Port Platform Device Initialization 1.1.11. FME IOCTLs 1.1.12. Port IOCTLs
1.1.6. Driver Organization x
1.1.6.1. PCIe Module Device Driver 1.1.6.2. PCIe Module Device Driver Functions 1.1.6.3. FME Platform Module Device Driver 1.1.6.4. FME Platform Module Device Driver Functions 1.1.6.5. Port Platform Module Device Driver 1.1.6.6. Port Platform Module Device Driver Functions
1.1.8. PCIe Driver Enumeration x
1.1.8.1. Enumeration Data Structures 1.1.8.2. Enumeration Flow
1.1.9. FME Platform Device Initialization x
1.1.9.1. FME Platform Device Data Structures 1.1.9.2. FME Platform Device Initialization Flow
1.1.10. Port Platform Device Initialization x
1.1.10.1. Port Platform Device Data Structures 1.1.10.2. Port Platform Device Initialization Flow
1.2. sysfs Files x
1.2.1. FME Header sysfs files 1.2.2. FME Thermal Management sysfs files 1.2.3. FME Power Management sysfs files 1.2.4. FME Global Error sysfs files 1.2.5. FME Partial Reconfiguration sysfs files 1.2.6. FME Global Performance sysfs files 1.2.7. Port Header sysfs files 1.2.8. Port AFU Header sysfs files 1.2.9. Port Error sysfs files
1. OPAE Intel® FPGA Linux Device Driver Architecture

1.1.8.1. Enumeration Data Structures


enum fpga_id_type { 
	PARENT_ID, 
	FME_ID, 
	PORT_ID, 
	FPGA_ID_MAX 
}; 

static struct idr fpga_ids[FPGA_ID_MAX];

struct fpga_chardev_info { 
	const char *name; 
	dev_t devt; 
}; 

struct fpga_chardev_info fpga_chrdevs[] = { 
	{ .name = FPGA_FEATURE_DEV_FME }, 
	{ .name = FPGA_FEATURE_DEV_PORT }, 
};

static struct class *fpga_class;

static struct pci_device_id cci_pcie_id_tbl[] = { 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_MCP),}, 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_MCP),}, 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_SKX_P),}, 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_SKX_P),}, 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_DCP),}, 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_DCP),}, 
	{0,} 
}; 

static struct pci_driver cci_pci_driver = { 
	.name = DRV_NAME, 
	.id_table = cci_pcie_id_tbl, 
	.probe = cci_pci_probe, 
	.remove = cci_pci_remove, 
	.sriov_configure = cci_pci_sriov_configure 
};

struct cci_drvdata { 
	int device_id; 
	struct device *fme_dev; 
	struct mutex lock; 
	struct list_head port_dev_list; 
	int released_port_num; 
	struct list_head regions; 
};

struct build_feature_devs_info { 
	struct pci_dev *pdev; 
	void __iomem *ioaddr; 
	void __iomem *ioend; 
	int current_bar; 
	void __iomem *pfme_hdr; 
	struct device *parent_dev; 
	struct platform_device *feature_dev; 
};
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