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1.1. Hardware and Software Requirements
1.2. Generating the Design
1.3. Directory Structure
1.4. Simulating the Design Example Testbench
1.5. Compiling the Compilation-Only Project
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the eCPRI Intel FPGA IP Design Example
1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
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2.3. Simulation Design Example
The eCPRI design example generates a simulation testbench and simulation files that instantiates the eCPRI Intel® FPGA IP core when you select the Simulation or Synthesis & Simulation option.
Figure 9. eCPRI Intel® FPGA IP Simulation Block Diagram
Note: The Nios® V Subsystem block is not present in the design example generated for Arria® 10 and Agilex™ 7 F-tile devices.
Figure 10. eCPRI Intel® FPGA IP Simulation Block Diagram for Agilex 5 Devices
In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit and receive packets.
The successful test run displays output confirming the following behavior:
- The client logic resets the IP core.
- The client logic waits for the RX datapath alignment.
- The client logic transmits packets on the Avalon-ST interface.
- Receive and checks for the content and correctness of the packets.
- Display "Test PASSED" message.