eCPRI Intel® FPGA IP Design Example User Guide

ID 683837
Date 8/16/2024
Public

2.3. Simulation Design Example

The eCPRI design example generates a simulation testbench and simulation files that instantiates the eCPRI Intel® FPGA IP core when you select the Simulation or Synthesis & Simulation option.
Figure 9.  eCPRI Intel® FPGA IP Simulation Block Diagram
Note: The Nios® V Subsystem block is not present in the design example generated for Arria® 10 and Agilex™ 7 F-tile devices.
Figure 10.  eCPRI Intel® FPGA IP Simulation Block Diagram for Agilex 5 Devices

In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit and receive packets.

The successful test run displays output confirming the following behavior:
  1. The client logic resets the IP core.
  2. The client logic waits for the RX datapath alignment.
  3. The client logic transmits packets on the Avalon-ST interface.
  4. Receive and checks for the content and correctness of the packets.
  5. Display "Test PASSED" message.