eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 8/16/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. eCPRI IP Design Example Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide

2.3. Simulation Design Example

The eCPRI design example generates a simulation testbench and simulation files that instantiates the eCPRI Intel® FPGA IP core when you select the Simulation or Synthesis & Simulation option.
Figure 9.  eCPRI Intel® FPGA IP Simulation Block Diagram
Note: The Nios® V Subsystem block is not present in the design example generated for Arria® 10 and Agilex™ 7 F-tile devices.
Figure 10.  eCPRI Intel® FPGA IP Simulation Block Diagram for Agilex 5 Devices

In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit and receive packets.

The successful test run displays output confirming the following behavior:
  1. The client logic resets the IP core.
  2. The client logic waits for the RX datapath alignment.
  3. The client logic transmits packets on the Avalon-ST interface.
  4. Receive and checks for the content and correctness of the packets.
  5. Display "Test PASSED" message.
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